AD8326ARE Analog Devices Inc, AD8326ARE Datasheet - Page 6

• Manufacturer Part Number: AD8326ARE
• Description: IC LINE DVR CATV PROG 28-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Line Driver, Transmitterr

Specifications of AD8326ARE

• Rohs Status: RoHS non-compliant
• Applications: CATV
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
• For Use With: AD8326ARE-EVAL - BOARD EVAL FOR AD8326 TSSOP

AD8326
Pin No.
1
2
3
4, 28
5, 9, 10, 19,
20, 23, 27
6
7
8, 12, 17
11, 13, 16, 18,
22, 24
14
15
21
25
26
Mnemonic
DATEN
SDATA
CLK
GND
V
TXEN
SLEEP
NC
V
OUT–
OUT+
BYP
V
V
CC
EE
IN+
IN–
Description
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic
0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta-
neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch
(holds the previous gain state) and simultaneously enables the register for serial data load.
Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the
internal register with the MSB (Most Significant Bit) first and ignored.
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-
slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to
the slave. This requires the input serial data word to be valid at or before this clock transition.
Common External Ground Reference
Common Positive External Supply Voltage. A 0.1 F capacitor must decouple each pin.
Transmit Enable pin. Logic 1 powers up the part.
Low Power Sleep Mode. In the Sleep mode, the AD8326’s supply current is reduced to 4 mA. A
Logic 0 powers down the part (High Z
No Connection to these pins.
Common Negative External Supply Voltage. A 0.1 F capacitor must decouple each pin.
Negative Output Signal
Positive Output Signal
Internal Bypass. This pin must be externally ac-coupled (0.1 F capacitor).
Noninverting Input. DC-biased to approximately V
0.1 F capacitor.
Inverting Input. DC-biased to approximately V
PIN FUNCTION DESCRIPTIONS
DATEN
SDATA
SLEEP
PIN CONFIGURATION
TXEN
OUT–
GND
CLK
V
V
V
V
V
NC
NC
CC
CC
CC
EE
EE
10
11
12
13
14
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
(Not to Scale)
AD8326
TOP VIEW
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OUT
GND
V
V
V
V
V
V
BYP
V
V
V
NC
V
OUT+
CC
IN–
IN+
EE
CC
EE
CC
CC
EE
EE
State) and a Logic 1 powers up the part.
CC
/2. Should be ac-coupled with a 0.1 F capacitor.
CC
/2. Should be ac-coupled with a