TMPM380FWFG Toshiba, TMPM380FWFG Datasheet - Page 501
TMPM380FWFG
Manufacturer Part Number
TMPM380FWFG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM380FWDFG.pdf
(700 pages)
Specifications of TMPM380FWFG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
12K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
5V
Cpu Mhz
40
Ssp (ch) Spi
2
I2c/sio (ch)
2
Uart/sio (ch)
5
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
18
16-bit Timer / Counter
8
Motor / Igbt Control
Y
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM380FWFG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
- Current page: 501 of 700
- Download datasheet (5Mb)
17 Watchdog Timer (WDT)
17.4 Operation
The watchdog timer generates the INTWDT or an internal reset after a lapse of the detection time
specified by the WDMOD <WDTP2: 0> register. Before generating the INTWDT or an internal reset,
the binary counter for the watchdog timer must be cleared to "0" using software (instruction). If the
CPU malfunctions (runaways) due to noise or other disturbances and cannot execute the instruction
to clear the binary counter, the binary counter overflows and the non-maskable interrupt by the
INTWDT or an internal reset is generated. The CPU is able to recognize the occurrence of a
malfunction (runaway) by identifying the non-maskable interrupt and to restore the faulty condition to
normal by using a malfunction (runaway) countermeasure program.
The watchdog timer begins operation immediately after a reset is cleared.
on the WDMOD <I2WDT> setting. Before putting it in IDLE mode, WDMOD <I2WDT> must be set to
an appropriate setting, as required.
In STOP mode, the watchdog timer is reset and in an idle state. In IDLE mode, its operation depends
(Note 1) The counter of the watchdog timer stops at the debug mode.
Example:
1. To clear the binary counter
2. To set the detection time of the watchdog timer to 2
3. To disable the watchdog timer.
WDMOD ← 1 0 0 1
WDMOD ← 0
WDCR
WDCR
← 0 1 0 0 1 1 1 0
← 1 0 1 1 0 0 0 1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
− − − − − − −
TMPM380/M382 - 6 / 6 -
− − − −
Writes the clear code
Clears WDTE to "0"
Writes the disable code (0xB1)
17
/f
SYS.
(0x4E)
TMPM380/M382
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