TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 108

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

CG
5.6. De-Skew Circuit
5.6.1. Theory of Operation
Figure 5-9 shows basic concepts of clock de-skew circuit. The module “dll_dskw1” is designed as follows.
A programmable delay line is implemented to delay the signal from CIN to OUT.
Whenever CIN input detect the clock edge, internal phase comparator starts to monitor both REF and SCK input for the
clock edge. If SCK input detects the clock edge earlier than REF input, it decreases the delay value and if it is opposite, it
increases the delay value. By this way, the pulse edge of P2 and P3 will be matched precisely.
For the delay line, Z7DELAYF ASIC delay line is used. It has 512 resolutions and each delay unit has 50 ps typical delay.
In the full range of operational condition, the unit delay might vary from 30 ps to 90 ps. Therefore, the maximum adjustable
range is about 15 ns.
5.6.2. DDR Clock De-Skew
The range of DDR Clock is from 100 MHz to 200 MHz. In terms of period, it is from 5 ns to 10 ns. Therefore, the
“dll_dskw1” module can be used with straightforward manner. Figure 5-10 shows the DDR Clock De-Skew circuit for
TX4939.
Rev. 3.1 November 1, 2005
Global
Clock
Tree
DDRCLK
CTS
DDR Internal Logic
Figure 5-10 Structure of DDR Clock De-Skew Circuit
Figure 5-9 Concept of Clock De-Skew Circuit
ALL DDR
ALL DDR
Q
LOGIC
LOGIC
CIN
SCK
RST
D
“dll_dskw1”
EN
5-14
D
Q
OUT
CIN
SCK
REF
“dll_dskw1”
=
Reference
Same
Delay
OUT
REF
Toshiba RISC Processor
Mother Board
Motherboard
DRCKP
DRCKM
DRCKOUT
DRCKREF
TX4939
5
5
5
5