TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 141

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Configuration
7.2.1. Chip Configuration Register (CCFG)
For the bit fields whose initial values are set by boot configuration (refer to Section 4.2), the initial input signal level and the
corresponding register value are indicated.
Rev. 3.1 November 1, 2005
M66EN
PCI66
R/W
R/O
WR
63
55
47
39
31
23
15
0
7
SYSSP
SA[4:3]
R/O
DMAACK[2]
PCIMODE
TOE
R/W
R/O
62
54
46
38
30
22
14
0
6
RESERVED
Reserved
Reserved
ACKSEL
SADB[6]
SADB[2]
PCIARB
R/O
R/O
61
53
45
37
29
21
13
5
Figure 7-1 Chip Configuration Register
SADB[3]
ROMW
SSCG
SA[5]
R/O
R/O
60
52
44
36
28
20
12
{ DMAACK[1], DMAACK[1:0] }
4
RESERVED
RESERVED
SADB[15:8]
BCFG[7:0]
R/O
YDIVMODE
Reserved
7-3
R/O
RO
59
51
43
35
27
19
11
3
0
PCIBOOT
MULCLK
SADB[7]
ENDIAN
SADB[4]
SA[2:0]
R/O
R/O
58
50
42
34
26
18
10
2
GTOT
2'b11
R/W
ARMODE
SADB[0]
WDRST
PTSEL
R/W
R/W
R/W
57
49
41
33
25
17
9
1
0
Toshiba RISC Processor
WDREXEN
ACEHOLD
~SADB[5]
TINTDIS
SADB[1]
BESEL
BEOW
RW1C
R/W
R/W
R/O
R/O
56
48
40
32
24
16
0
8
0
1
0xE000
: Default
: Default
: Default
: Default
: Default
: Default
: Default
: Default
: R/W
: R/W
: R/W
: R/W
: R/W
: R/W
: R/W
: R/W
TX4939
7
7