TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 142

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Configuration
Rev. 3.1 November 1, 2005
63:43
42
41
40
39:32
31:27
26:25
24
23
22
21
20
Bit
⎯
PCIBOOT
WDRST
WDREXEN
BCFG[7:0]
⎯
GTOT
TINTDIS
PCI66
PCIMODE
⎯
SSCG
Mnemonic
Reserved
PCI Boot
Configuration
Watchdog
Reset
Status
Watchdog
Reset
External
Output
Boot
Configuration
Reserved
G-Bus
Timeout
Time
Disable
TX49/H4 Core
Timer
Interrupt
PCI 66MHz
Mode
Host/Satellite
Control
Reserved
SSCG Control Specifies whether the Spread Spectrum Modulator is
Field Name
Table 7-2 Chip Configuration Register
⎯
PCI Boot Option
0 = PCI Boot off
1 = PCI Boot on
Watch Dog Reset Status (Initial Value 0, RW1C)
Indicates that a watchdog reset has occurred. Initialized
when RESET* is asserted.
0 = No watchdog reset has occurred.
1 = A watchdog reset has occurred
Watch Dog Reset External Enable (Initial Value 0, R/W)
Specifies whether to assert the WDRST* signal at a
watchdog reset.
Initialized when RESET* is asserted.
0 = Do not assert the WDRST* signal.
1 = Assert the WDRST* signal.
Set to 1 at a reset if the corresponding SADB[15:8] signal is
high.
Set to 0 at a reset if the corresponding SADB[15:8] signal is
low.
⎯
Specifies the number of G-Bus clock (GBUSCLK) cycles
after which a bus timeout error will occur on the internal bus
(G-Bus) of the TX4939.
11 = 4096 GBUSCLK
10 = 2048 GBUSCLK
01 = 1024 GBUSCLK
00 = 512 GBUSCLK
Indicates a value for indicating whether to enable the
TX49/H4 internal timer interrupt.
This signal is inverted signal of TIMEREN
0: The TX49/H4 internal timer interrupt is enabled.
1: The TX49/H4 internal timer interrupt is disabled.
Used to inform the device connected to the PCI bus that a 66
MHz operation is to be performed.
0 = Perform a 33 MHz operation.
1 = Perform a 66 MHz operation.
Indicates the PCI Host/Satellite selection setting
1 = Host
0 = Satellite
⎯
bypassed
0 = SSCG Disabled (Bypass)
1 = SSCG Enabled
7-4
Description
Toshiba RISC Processor
⎯
SADB[7]
0
0
SADB[15:8]
⎯
2'b11
~SADB[5]
M66EN
DMAACK[2]
⎯
SA[5]
Initial Value
⎯
R/O
RW1C
R/W
R/O
⎯
R/O
R/O
R/O
⎯
R/O
R/W
TX4939
R/W
7
7