TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 143

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Configuration
Rev. 3.1 November 1, 2005
19:17
16
15
14
13
12:10
9
8
7:6
5
4
Bit
MULCLK
BEOW
WR
TOE
PCIARB
YDIVMODE
PTSEL
BESEL
SYSSP
ACKSEL
ROMW
Mnemonic
CPUCLK
Frequency
Multiplication
Factor
Write-Access
Bus Error
Watchdog
Timer Mode
G-Bus
Timeout Error
Detection
PCI Arbiter
Selection
GBUSCLK
Frequency
Division Ratio
PC Trace
Mode
BE function
SYSCLK
frequency
division ratio
Boot ACK* I/P Specifies the access mode for external bus controller
Boot ROM
Bus Width
Field Name
Table 7-2 Chip Configuration Register
Indicates information about the frequency multiplication
factor of the TX49/H4 core clock (CPUCLK) to the MSTCLK.
This field is set with a result of encoding an initial input value
at SA[2:0].
The PLL incorporated in the TX4939 multiplies the MSTCLK
and supplies the resulting frequency to the TX49/H4 core.
The value set in YMULCLK [4:0] is reflected in the EC field of
the TX49/H4 core Configuration register.
MULCLK[2:0] ==> YMULCLK[4:0] = ND[4:0]
The following equation defines the CPUCLK frequency as a
function of the MSTCLK frequency and YMULCLK:
CPUCLK(f) = (25 x YMULCLK x MSTCLK(f) ) / 36
Indicates that a timeout error has occurred in the internal bus
(G-Bus) during a write bus transaction of the TX49/H4 core.
This bit corresponds to interrupt No. 2 in the interrupt
controller.
0 = No error has occurred.
1 = An error has occurred.
Specifies how information will be reported in watchdog timer
mode.
0 = Generate an NMI exception.
1 = Generate a watchdog reset.
Specifies whether to detect and report a bus timeout error in
the internal bus (G-Bus) of the TX4939.
0 = Do not detect or report a bus timeout error.
1 = Detect and report a bus timeout error.
Indicates the PCI bus arbiter selection setting
0 = Select external PCI bus arbiter
1 = Select built-in PCI bus arbiter
Specifies the frequency division ratio of the GBUS clock
output (GBUSCLK) frequency to the clock frequency
(CPUCLK) of the TX49/H4 core.
000:GBUSCLK frequency = CPUCLK frequency ÷ 2
001:GBUSCLK frequency = CPUCLK frequency ÷ 3
110:GBUSCLK frequency = CPUCLK frequency ÷ 5
111:GBUSCLK frequency = CPUCLK frequency ÷ 6
PC Trace Mode Enable
0 = PC Trace Disable
1 = PC Trace Enable
Specifies the function of BE[1:0]*/BWE[1:0]* pins upon
booting
0: BE[1:0]* (Byte Enable)
1: BWE[1:0]* (Byte Write Enable)
Indicates the frequency division ratio of the SYSCLK
frequency to the G-Bus clock frequency (GBUSCLK).
00: SYSCLK frequency = GBUSCLK frequency ÷ 4
01: SYSCLK frequency = GBUSCLK frequency ÷ 3
10: SYSCLK frequency = GBUSCLK frequency ÷ 5
11: SYSCLK frequency = GBUSCLK frequency ÷ 6
channel0
0 = External ACK mode
1 = Normal mode
Specifies the data bus width when booting from a memory
device connected to the local bus controller
ROMW = 1'b0 = 16 bits
ROMW = 1'b1 = 8 bits
MULCLK[2:0]
000
001
010
011
100
101
110
111
ND[4:0]
5'b01000
5'b 01001
5'b 01010
5'b 01011
5'b 01100
5'b 01101
5'b 01110
5'b 00111
7-5
Description
800 MHz
Reserved
Reserved
533 MHz
PLL#2
600 MHz
666 MHz
733 MHz
Reserved
CPU Clock
300 MHz
333 MHz
366 MHz
400 MHz
Reserved
Reserved
Reserved
266 MHz
Toshiba RISC Processor
SA[2:0]
0
0
0
SADB[6]
{
DMAACK[1],
DMAACK[1:0]
}
SADB[0]
SADB[1]
SA[4:3]
SADB[2]
SADB[3]
Initial Value
R/O
RW1C
R/W
R/W
R/O
R/O
R/W
R/O
R/O
R/O
R/O
TX4939
R/W
7
7