TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 167
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TX4939XBG-400
Manufacturer:
NSC
Quantity:
872
Company:
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA
Quantity:
10 440
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
- Current page: 167 of 740
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Rev. 3.1 November 1, 2005
Note 1:
Note 2:
Interrupt
Number
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
0
1
2
3
4
5
6
7
8
9
Value of S in the expression 6’b0SSSS1 represents the selected interrupt source. In case IP[2] is
“1”, one or more than one of SSSS should be “1”.
If these four interrupt signal are used for PCI, all of them should be programmed as Level detect
mode. Edge detect mode is provided as general purpose interrupt control.
No Interrupt
DDR
Tx49 Write Timeout
INT0
INT1
INT2
Ether0
VIDEO
CIR
SIO0
DMA0[0]
DMA0[1]
DMA0[2]
DMA0[3]
IRC
PDMAC0
TMR0
TMR1
TMR2
ATA0
ATA1
ACLC
DMA1[0]
DMA1[1]
DMA1[2]
DMA1[3]
Cipher
INTA (Note 2)
INTB (Note 2)
INTC (Note 2)
INTD (Note 2)
## Not For Use
## Reserved
I2C
SPI
## Reserved
PCIC1(PCI1ERR,PCI1PME)
PCI0ERR
PCI0PME
NANDC
ACLC_PME
RTC
RSA/RND
Ether1
SIO1
SIO2
SIO3
I2S
TMR3
TMR4
TMR5
Interrupt Source
Defined Number
Table 8-1 TX4939 Interrupt Sources
Edge/Level
Edge/Level
Edge/Level
Edge/Level
Edge/Level
Edge/Level
Edge/Level
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Low Active
Control
Detect
-
8-5
IRCS.CAUSE
####
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
0
1
2
3
4
5
6
7
8
9
(See 8.4.2)
IP[7:3]
Original Mode
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
0
1
2
3
4
5
6
7
8
9
IP[2]
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Toshiba RISC Processor
Compatible Mode
IP[7:2] (Note 1)
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b0SSSS1
6’b000000
TX4939
8
8
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