TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 201

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EBC
9.2.8.4.
The ACK* signal becomes an input signal when in the external ACK mode.
During a Read cycle, data is latched two clock cycles after assertion of the ACK* signal is acknowledged ( ). During a Write
cycle, assertion of the ACK* signal is acknowledged, SWE*/BWE* is deasserted three clock cycles later, then data is held
for one clock cycle after that ( ).
The ACK* input signal is internally synchronized. Due to internal State Machine restrictions, ACK* cannot be acknowledged
consecutively on consecutive clock cycles. External devices can assert ACK* across multiple clock cycles under the
following conditions.
During Single access, the ACK* signal can be asserted before the end of the cycle during which CE* is dasserted.
During Burst access, it is possible to assert the ACK* signal for up to three clock cycles during Reads and for up to five clock
cycles during Writes. If the ACK* signal is asserted for a period longer than this, it will be acknowledged as the next valid
ACK* signal.
Rev. 3.1 November 1, 2005
ACK*/READY
SWE*/BWE*
SADB [15:0]
AD [28:6]
SYSCLK
SA [5:0]
ACE*
input
ACK* Input Timing (External ACK Mode)
OE*
CE*
0
1
Acknowledge ACK*
2
EBCCRn.SHWT=0
Figure 9-9 ACK* Input Timing (Single Read/Write Cycle)
Single Read Cycle
3
ACK* Input Timing (Normal Mode, Page Mode )
4
2 clocks
5
Latch Data
6
7
9-11
8
9
10
11
12
Acknowledge ACK*
13
14
Single Write Cycle
EBCCRn.SHWT=0
Toshiba RISC Processor
15
3 clocks
16
4 clocks
17
18
19
TX4939
Rev 2.13
9
9