TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 228

no-image

TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TX4939XBG-400
Manufacturer:
NSC
Quantity:
872
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA
Quantity:
10 440
Part Number:
TX4939XBG-400
Manufacturer:
XILINX
0
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
NDFMC
10.3.3. Accessing NAND Flash Memory (General Procedure)
With the NDFMC, you can access NAND flash memory by controlling registers. The NDFMC also has an ECC calculation
function. See 10.4.1 for more information on ECC. This subsection describes the procedure for accessing NAND flash
memory.
To access NAND Flash Memory, following steps are required.
Rev. 3.1 November 1, 2005
STEP 1
Initialization
STEP 2
Preparation
STEP 3-X
Operation
STEP Last
(Note)
Write any Data to NDFSR, this initialize entire NAND Flash Controller.
Define the Write Pulse Width and Hold Time by setting NDFSPR register.
Write 0x0000 to NDFMCR followed by writing any value to NDFDTR, this operation generates
ND_LA assertion to update the value of external latch.
Select a NAND Chip by asserting ND_CE bit. ND_CS [1:0] provides additional selection for NAND
chips. Once select a NAND chip, do not change these three parameters until the end of entire
NAND access.
By using NDFMCR and NDFDTR register do the read/write operation for NAND device.
Repeat these operations.
First, set signal pattern and command mode in the NDFMCR, then either read or write NDFDTR to
access NAND flash memory.
Reading from NDFDTR invokes a read cycle to external NAND flash memory. The read cycle to
NDFDTR also ends when the read cycle to external NAND flash memory ends. During this bus
transaction, assertions of ND_LA and ND_RE* are unconditional.
Writing to NDFDTR invokes a write cycle to external NAND flash memory. The write cycle to
NDFDTR also ends when the write cycle to external NAND flash memory ends. During this bus
transaction, the assertion of ND_LA is unconditionally, but the assertion of ND_WE* is conditional.
In case of “COMMAND” or “ADDRESS” phase with ALE=1 or CLE=1, the assertion of ND_WE* is
unconditional. In other cases, the assertion of ND_WE* is controlled by WE bit in NDFMCR
register. (See Note below)
Deassert ND_CE bit
Write operation to NDFMCR will complete when the value is set to this register.
Only the CE bit contents propagate to external terminal on the fly. However, the other signal bits
are just set in the register only. They will not propagate to external latch at that time. Because of
this, an intentional synchronization is required as UPDATE operation in some cases.
For example, after ALE signal de-assertion, followed ND_RE* assertion should wait certain period.
In this case, UPDATE operation with only ND_LA assertion is required.
10-4
Toshiba RISC Processor
TX4939
10
10

Related parts for TX4939XBG-400