TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 24

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Index
Rev. 3.1 November 1, 2005
Table 7-4 Pin Configuration Register ....................................................................................................................... 7-9
Table 7-5 Timeout Error Access Register ...............................................................................................................7-11
Table 7-6 Clock Control Register ........................................................................................................................... 7-13
Table 7-7 G-Bus Arbiter Control Register .............................................................................................................. 7-16
Table 7-8 Register Address Mapping Register....................................................................................................... 7-17
Table 7-9 DLL De-Skew Control Register .............................................................................................................. 7-18
Table 7-10Bit Field Definitions of MCLKOSC Register .......................................................................................... 7-19
Table 7-11 Bit Field Definitions .............................................................................................................................. 7-20
Table 7-12 GPIOMR1 Register .............................................................................................................................. 7-21
Table 7-13 GPIODR1 Register .............................................................................................................................. 7-22
Table 7-14 GPIOMR2 Register .............................................................................................................................. 7-23
Table 7-15 GPIODR2 Register .............................................................................................................................. 7-24
Table 8-1 TX4939 Interrupt Sources ........................................................................................................................ 8-5
Table 8-2 Interrupt Levels ........................................................................................................................................ 8-6
Table 8-3 Interrupt Notification to IP[7:2] of the CP0 Cause Register ...................................................................... 8-7
Table 8-4 Interrupt Notification to IP[7:2] of the CP0 Cause Register ...................................................................... 8-7
Table 8-5 Interrupt Control Registers....................................................................................................................... 8-9
Table 8-6 Interrupt Detection Enable Register ....................................................................................................... 8-10
Table 8-7 Interrupt Source and Cause IP Binding Register ....................................................................................8-11
Table 8-8 Interrupt Detection Mode Register 0 ...................................................................................................... 8-12
Table 8-9 Interrupt Detection Mode Register 1 ...................................................................................................... 8-13
Table 8-10 Interrupt Detection Mode Register 2 .................................................................................................... 8-14
Table 8-11 Interrupt Detection Mode Register 3 .................................................................................................... 8-15
Table 8-12 Interrupt Mask Level Register .............................................................................................................. 8-16
Table 8-13 Interrupt Level Register Field Definition (CASE of IRLVL0) ................................................................. 8-17
Table 8-14 Interrupt Edge Dectection Clear Register ............................................................................................ 8-18
Table 8-15 Interrupt Pending Register 0 ................................................................................................................ 8-19
Table 8-16 Interrupt Pending Register 1 ................................................................................................................ 8-20
Table 8-17 Interrupt Current Status Register ......................................................................................................... 8-21
Table 8-18 Interrupt Request Flag Register 0 ........................................................................................................ 8-22
Table 8-19 Interrupt Request Flag Register 1 ........................................................................................................ 8-23
Table 8-20 Interrupt Requests Polarity Control Register........................................................................................ 8-24
Table 8-21 Interrupt Request Control Register ...................................................................................................... 8-25
Table 8-22 Interrupt Request Internal Interrupt Mask Register .............................................................................. 8-26
Table 8-23 Interrupt Request External Interrupt Mask Register ............................................................................. 8-27
Table 8-24 Interrupt Debug Register 0................................................................................................................... 8-27
Table 8-25 Interrupt Debug Register 1................................................................................................................... 8-28
Table 8-26 Interrupt Debug Enable Register ......................................................................................................... 8-28
Table 9-1 External Bus Control Registers ................................................................................................................ 9-2
Table 9-2 Boot Configuration for Channel 0 (Subset of Table 4-1 Boot Configuration Details) ................................ 9-2
Table 9-3 Address Mask .......................................................................................................................................... 9-3
Table 9-4 Address Bit Correspondin in the 16-bit Mode........................................................................................... 9-4
Table 9-5 Address Bit Correspondin in the 8-bit Mode............................................................................................. 9-4
Table 9-6 Operation Mode ....................................................................................................................................... 9-5
Table 9-7 External Bus Controller (EBUSC) Registers ......................................................................................... 9-15
Table 9-8 External Bus Channel Control Register ................................................................................................. 9-16
Table 10-1 NDFMC Registers................................................................................................................................ 10-3
Table 10-2 Mnemonic Command Parameter for NDFDTR .................................................................................... 10-3
Table 10-3 Mnemonic Parameter for NDFMCR ..................................................................................................... 10-3
Table 10-4 NAND Flash Memory Data Transfer Register (NDFDTR) .................................................................. 10-13
Table 10-5 NAND Flash Memory Mode Control Register (NDFMCR) ................................................................. 10-14
Table 10-6 NAND Flash Memory Status Register (NDFSR) ................................................................................ 10-15
Table 10-7 NAND Flash Memory Interrupt StatusRegister (NDFISR).................................................................. 10-15
Table 10-8NAND Flash Memory Interrupt Mask Register (NDFIMR)................................................................... 10-16
Table 10-9 NAND Flash Memory Strobe Pulse Width Register (NDFSPR) ......................................................... 10-17
Table 11-1 Non-Exposed Internal Registers ...........................................................................................................11-3
Table 11-2 Exposed Internal Registers ...................................................................................................................11-3
Table 11-3 Address Mapping of Exposed Registers ...............................................................................................11-4
Table 11-4 Control IO ports.....................................................................................................................................11-5
Table 11-5 RTCCTL Command Code .....................................................................................................................11-5
Table 11-6 Bit Field Definitions ...............................................................................................................................11-8
Table 12-1 VPR Registers ..................................................................................................................................... 12-9
Table 12-2 Control and Status Register (CSR) .................................................................................................... 12-10
Table 12-3 ControlA Register (CtrlA) ....................................................................................................................12-11
Table 12-4 ControlB Register (CtrlB) ................................................................................................................... 12-12
Table 12-5 Initial Descriptor Pointer Register (IDESPtr) ...................................................................................... 12-12
xx
Toshiba RISC Processor
TX4939