TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 249

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

RTC
11.3.2.
RTC has four register ports. Only word access, i.e. LW or SW, are allowed. Other type of access may cause unexpected
result. Table 11-4 shows these registers.
Note: These registers are 32-bits register but only lower 8-bits are used. Upper 24-bits are reserved. Upper 24-bits return
“0” for read operation.
11.3.3.
Data Read from this port returns the status and issue command before. Data Write to this port issues command if the
command code is valid.
Following Table 11-5 describes detail of command code for RTCCTL register.
Rev. 3.1 November 1, 2005
Offset Address
RTC Controller
0xFB00
0xFB04
0xFB08
0xFB0C
Operation
NOP
Get Time
Set Time
Get Alarm
Set Alarm
NOP
NOP
NOP
RTCCTL
Field Definition
R/W
DEFAULT
RTCCTL
RTCCTL[7]
RTCCTL[6]
RTCCTL[5]
RTCCTL[4:3]
RTCCTL[2:0]
RTC IP Control Registers
Control and Status Register (RTCCTL)
CODE
0
1
2
3
4
5
6
7
Register Size (bit)
32
32
32
32
ALME
R/W
X
Bit
1
1
1
2
3
7
Description
This command can be used to set or reset the ALARM Bit safely.
Copy RTC [47:0] contents to RWB [47:0] in next 32.768 KHz rising clock edge.
RTCADR [7:0] will be set to zero.
Copy RWB [47:16] contents to RTC [47:16] in next 32.768 KHz rising clock edge.
The RTC [15:0] will be cleared to zero. In addition, RTCADR [7:0] will be reset to zero.
Copy the ALARM [47:16] contents to RWB [47:16] in next 32.768 KHz rising clock edge.
RTCADR [7:0] will be set to zero.
Copy RWB [47:16] contents to ALARM [47:16] in second 32.768 KHz rising clock edge.
RTCADR [7:0] will be set to zero. Same time, the alarm detection FF will be reset.
This command can be used to set or reset the ALARM Bit safely.
This command can be used to set or reset the ALARM Bit safely.
This command can be used to set or reset the ALARM Bit safely.
ALMD
R/W
X
Description
Alarm Enable Control. "1" on this bit enables ALARM function to detect alarm and
generate an interrupt.
Alarm Detection Signal. If RTC[47:16] matches with ALARM [47:16], this FF will be
set to "1" and hold this value until (1) Set Alarm command issued or (2) Alarm Enable
Control is disabled. This bit can be used form alarm test. When this bit set to "1",
pseudo alarm signal will be generated that is same as real alarm detection (only if
RTCCTL[7] is set). Write “0” to this bit will do nothing.
BUSY. This bit will be set to "1" right after command write to RTCCTL and return to
"0" when the command operation complete.
Reserved.
Command for register transferring. See Table 11-5 in detail.
Table 11-5 RTCCTL Command Code
Register Symbol
RTCCTL
RTCADR
RTCDAT
RTCTBC
6
Table 11-4 Control IO ports
Figure 11-2 Port RTCCTL
BUSY
R/O
0
5
11-5
Reserved
R/O
0
Register Name
Control and Status Register
Address Register
Data port to access the contents of RTC registers
Time Base Corrector Register
4
Reserved
R/O
0
3
COMMAND
R/W
X
2
Toshiba RISC Processor
X
1
0xFB00
X
0
TX4939
11
11