TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 252
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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RTC
The 7-BIT Counter counts 0 to 127, so that the output of 7-BIT_Comparator (i.e. GT) generates a same number of "1"
signals with the value of COMP [6:0]. The control logic controls 12-BIT Counter. In normal case, this 12-BIT Counter
counts 0 to 4095.
When the signal GT is 1 and PM equal 1, 12-BIT Counter will count …,4094,4095,0,0,1,2,… (repeat 0 twice). On the
contrary, when the signal GT is 1 and PM equal 0, 12-BIT Counter will count …,4094,4095,0,2,3,… (skip 1). By this way,
the time base correction will be done.
Rev. 3.1 November 1, 2005
7
6:0
Bit Field
PM
COMP[6:0]
Symbol
Direction of Correction (Default = 0)
PM = 1: Delay the time base with COMP [6:0] (unit PPM)
PM = 0: Advance the time base with COMP [6:0] (unit PPM)
Compensation Value (Default = 0)
COMP [6:0] can be 0 to 127 (unsigned integer)
If COMP [6:0] is set non-zero value, time base correction will happen. Direction of Correction is
defined bt the value of PM bit.
Table 11-6 Bit Field Definitions
11-8
Description
Toshiba RISC Processor
TX4939
11
11
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