TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 266

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Video Port
12.3.7. Descriptor Format
All Video Port’s descriptors are 32-bit, must use LW and SW to access to these descriptor.
Rev. 3.1 November 1, 2005
Field
31:0
Field
31:2
1:0
Field
31
30:8
7:3
2:1
0
Name
DMAGA[31:0]
Name
nxtptr[31:2]
-
Name
----
Bcount[22:0]
---
Error
OWN
Description
Input/Output DMA Address Descriptor
Next Descriptor Pointer Descriptor
Control 1 Descriptor
Control 2 Descriptor
Description
DMA G-Bus Address[31:0]
Byte addressable
Description
Address of the next descriptor.
Null ('h0000_0000) = End of chain.
Reserved.
Description
Reserved.
Byte Count - up to 8M byte
23’h000000 = 1 byte
23’h000001 = 2 bytes
23’h000002 = 3 bytes
……
23’h7FFFFF = 8M bytes
- For Capture mode minimum byte count must be 8 bytes.
Reserved.
VPC will set these bits when there is an error occurred when process this Descriptor
00 = no error
01 = Underflow/Overflow error
10 = reserved.
11 = reserved.
When error occurred, DMA engine will skip the rest of the operation until it see end of
Descriptor. Before starting process next descriptor.
When set, indicates that the descriptor is owned by VPC controller. When reset, indicates
that the descriptor is owned by the CPU. VPC controller clears this bit when it completes the
DMA.
Table 12-10 Next Descriptor Pointer Descriptor
Table 12-9 Input Source Address Descriptor
Table 12-8 VPC Descriptor Table
Table 12-11 Control 1 Descriptor
12-14
Toshiba RISC Processor
Offset
‘h00/’h08
‘h04/’h0c
‘h08/’h10
‘h0c/’h14
TX4939
12
12