TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 273

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Toshiba RISC Processor
TMR
TX4939
13.3.3. Counter
Each channel has an independent 32-bit counter. Set the Timer Count Enable bit (TMTCRn.TCE) and the 32-bit counter will
start counting.
Clear the Timer Count Enable bit to stop the counter. If the Counter Reset Enable bit (TMTCRn.CRE) is set, then the counter
will be cleared also. The Watchdog Timer Disable bit (TMWTRM2.WDIS) must be set in order to stop and clear this counter
when in the Watch Dog Timer mode.
Also, reading the Timer Read Register (TMTRR) makes it possible to fetch the counter value.
13.3.4. Interval Timer Mode
The Interval Timer mode is used to periodically generate interrupts. Setting the Timer Mode field (TMTCRn.TMODE) of the
Timer Control Register to “00” sets the timer to the Interval Timer mode. This mode can be used by all timers.
When the count value matches the value of Compare Register A (TMCPRAn), the Interval Timer TMCPRA Status bit
(TMTISRn.TIIS) of the Timer Interrupt Status Register is set. When the Interval Timer Interrupt Enable bit (TMITMRn.TIIE)
of the Interval Timer Mode Register is set, timer interrupts occur. When a “0” is written to the Interval Timer TMCPRA Status
bit (TMTISRn.TIIS), TIIS is cleared and timer interrupts stop.
If the Timer Zero Clear Enable bit (TMITMRn.TZCE) is set, the counter is cleared to 0 if the count value matches the
Compare Register A (TMCPRAn) value. Count operation stops when the Timer Zero Clear Enable bit (TMITMRn.TZCE) is
cleared.
The level of the TIMER[1:0] output signal stays in the initial state (Low) in this mode. Output is undefined when changing
from the Pulse Generator mode to this mode. Figure 13-3 shows an outline of the count operation and generation of
interrupts when in the Interval Timer mode and Figure 13-4 shows the operation when using an external input clock.
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Rev. 3.1 November 1, 2005
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