TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 279

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

TMR
13.6.1. Timer Control Register n (TMTCRn)
Rev. 3.1 November 1, 2005
Default
Default
Bit
31:8
7
6
5
4
3
2
1:0
Name
Name
TMTCR3 (0xFD00), TMTCR4 (0xFE00), TMTCR5 (0xFF00)
Type:
Type:
TMTCR0 (0xF000), TMTCR1 (0xF100), TMTCR2 (0xF200),
Mnemonic
TCE
CCDE
CRE
ECES
CCS
TMODE
31
15
30
14
Field Name
Reserved
Timer Counter
Enable
Counter Clock
Divider Enable
Counter Reset
Reserved
External Clock
Edge Select
Counter Clock
Select
Timer Mode
29
13
28
12
Reserved
27
11
Figure 13-7 Timer Control Register
Description
Timer Counter Enable (Default: 0)
This field controls whether the counter runs or stops.
When in the Watchdog mode, counter operation only stops when the
Watchdog Timer Disable bit (TMWTMR2.WDIS) of the Watchdog Timer
Mode Register is set. When the Watchdog Timer Disable bit is cleared, the
value of this Timer Count Enable bit becomes “0”, but the count continues.
0: Stop counter
1: Counter Operation
When TCE bit changes from 1 to 0, CRE value will be evaluated once. And
if and only if CRE value is 1, counter will be reset to 0.
Counter Clock Divide Enable (Default: 0)
This bit enables the divide operation of the internal clock (IMBUSCLK). The
counter stops if this bit is set to “0” when the internal bus clock is in use.
0: Disable
1: Enable
Counter Reset Enable (Default: 0)
The value of CRE will be evaluated once when TCE bit changes from 1 to
0. Counter value will be reset to zero if and only if CRE value is 1.
Such operation that TCE changes from 1 to 0 and same time, CRE
changes 0 to 1, by single register write, it will stop and reset the counter.
External Clock Edge Select (Default: 0)
This bit specifies the counter operation edge when using the counter input
signal (TCLK).
0: Falling edge of the counter input signal (TCLK)
1: Rising edge of the counter input signal (TCLK)
Counter Clock Select (Default: 0)
This bit specifies the timer clock.
0: Internal clock (IMBUSCLK)
1: External input clock (TCLK)
Please note that TX4939 does not support external clock
Timer Mode (Default: 00)
This bit specifies the timer operation mode.
11: Reserved
10: Watchdog Timer mode (Timer 2), Reserved (Timer 0, 1,3,4,5)
01: Pulse Generator mode (Timer 0, 1), Reserved (Timer 2,3,4,5)
00: Interval Timer mode
Table 13-3 Timer Control Register
26
10
25
9
13-11
RESERVED
24
8
TCE CCDE CRE
R/W
23
7
0
R/W
22
6
0
R/W
21
5
0
Reserved
Toshiba RISC Processor
20
4
ECES CCS
R/W
19
3
0
R/W
18
2
0
17
1
TMODE
R/W
⎯
R/W
R/W
R/W
⎯
R/W
R/W
R/W
TX4939
R/W
00
16
0
13
13