TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 287

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

TMR
13.6.8. Watchdog Timer Mode Register n (TMWTMRn)
Rev. 3.1 November 1, 2005
Bit
31:16
15
14:8
7
6:1
0
Default
Default
Name
Name
Type:
Type:
TMWTMR2 (0xF240)
Mnemonic
TWIE
WDIS
TWC
TWIE
R/W
31
15
0
30
14
Field Name
Reserved
Watchdog Timer
Signaling Enable
Reserved
Watchdog Timer
Disable
Reserved
Watchdog Timer
Clear
29
13
28
12
RESERVED
Figure 13-14 Watchdog Timer Mode Register
Table 13-10 Watchdog Timer Mode Register
27
11
Description
Timer Watchdog Enable (Default: 0)
This bit sets NMI signaling enable/disable either when in the Watchdog Timer
mode or during a reset. This bit cannot be cleared when the Watchdog Timer
Disable bit (WDIS) is “0”.
0: Disable (mask)
1: Enable
Watchdog Timer Disable (Default: 0)
Only when this bit is set can the counter be stopped by clearing the Watchdog
Timer Signaling Enable bit (TWIE) or by clearing the Timer Counter Enable bit
(TMTCR2.TCE) of the Timer Control Register.
Writing “0” to this bit is not valid. This bit can be cleared in either of the
following ways.
Clear the Watchdog Timer Interrupt Enable bit (TMWTMR2.TWIE).
Clear the Timer Counter Enable bit (TMTCR2.TCE) of the Timer Control
Register.
Watchdog Timer Clear (Default: 0)
Setting this bit to “1” clears the counter. Writing “0” to this bit is not valid. This
bit is always read as “0”.
26
10
25
9
13-19
RESERVED
24
8
RW1S
WDIS
23
7
0
22
6
21
5
20
4
Toshiba RISC Processor
0
19
3
18
2
17
1
R/W
⎯
R/W
⎯
R/W1S
⎯
R/W1C
TX4939
R/W1C
TWC
16
0
0
13
13