TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 306

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DMA
14.3.13. Transfer Stall Detection Function
If the period from when a certain channel last performs internal bus access to when the next internal bus access is
performed exceeds the Transfer Stall Detection Interval field (STLTIME) of the DMA Channel Control Register (DMCCRn),
the Transfer Stall Detection bit (STLXFER) of the DMA Channel Status Register (DMCSRn) is set. An error interrupt is
signalled if the Error Interrupt Enable bit (DMCCRn.INTENE) is set.
In contrast to other error interrupts, DMA transfer is not stopped. Normal DMA transfer is executed if bus ownership can
be obtained. Furthermore, clearing the Transfer Stall Detection field (STLXFER) resumes transfer stall detection as well.
Setting the Transfer Stall Detection Interval field (STLTIME) to “000” disables the Transfer Stall Detection function.
14.3.14. Arbitration Among DMA Channels
The DMA Controller has an on-chip DMA Channel Arbiter that arbitrates bus ownership among four DMA channels that
use the internal bus (G-Bus). There are two methods for determining priority: the round robin method and the fixed
priority method. (See Figure 14-8.) The Round Robin Priority bit (RRPT) of the DMA Master Control Register (DMMCR)
selects the priority method.
Fixed priority (DMMCR.RRPT = 0)
As shown below, Channel 0 has the highest priority and Channel 3 has the lowest priority.
Round Robin method (DMMCR.RRPT = 1)
The last channel to perform DMA transfer has the lowest priority.
Rev. 3.1 November 1, 2005
CH0 > CH1 > CH2 > CH3
□ After CH0 DMA transfer execution: CH1 > CH2 > CH3 > CH0
□ After CH1 DMA transfer execution: CH2 > CH3 > CH0 > CH1
□ After CH2 DMA transfer execution: CH3 > CH0 > CH1 > CH2
□ After CH3 DMA transfer execution: CH0 > CH1 > CH2 > CH3
Channel 0
Channel 3
Figure 14-8 DMA Channel Arbitration
b) Round Robin Priority is selected
Channel 1
a) Fixed Priority is selected
Channel 0
Channel 2
14-18
Channel 2
Channel 1
Toshiba RISC Processor
Channel 3
TX4939
14
14