TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 313

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DMA
Rev. 3.1 November 1, 2005
Bit
26
25
24
23
22
21
20
19
18:17
Mnemonic
DBINH
SBINH
CHRST
REVBYTE
ACKPOL
REQPL
EGREQ
CHDN
DNCTL
Field Name
Destination Burst
Inhibit
Source Burst
Inhibit
Channel Reset
Reverse Byte
Acknowledge
Polarity
Request Polarity
Edge Request
Chain Complete
DONE Control
Table 14-8 DMA Channel Control Register
Description
Destination Burst Inhibit (Default: 0)
During Dual Address transfer, this bit sets whether to perform Burst transfer
or Single transfer on a Write cycle to the address set from FIFO to DMDARn
when Burst transfer is set by DMCCRn.XFSZ. Refer to “14.3.8.2 Burst
Transfer During Dual Address Transfer” for more information.
The settings of this bit have no effect during Single Address transfers.
1: Multiple Single transfers are executed.
0: Burst transfer is executed.
Source Burst Inhibit (Default: 0)
During Dual Address transfer, this bit sets whether to perform Burst transfer
or Single transfer on a Read cycle to the FIFO from the address set to
DMSARn when Burst transfer is set by DMCCRn.XFSZ. Refer to “14.3.8.2
Burst Transfer During Dual Address Transfer” for more information.
The settings of this bit have no effect during Single Address transfers.
1: Multiple Single transfers are executed.
0: Burst transfer is executed.
Channel Reset (Default: 1)
This bit is used fo initializing channels. The DMCCRn.XFACT,
DMCCRn.CHNEN, and DMCSRn bits are all cleared. In addition, all channel
logic and interrupts from channels are cleared and bus ownership requests to
the DMA Channel Arbiter are also reset. The software must clear this bit
before operating a channel.
1: Reset channel
0: Enable channel
Reverse Bytes (Default: 0)
This bit specifies whether to reverse the byte order during a Dual Address
transfer when the Transfer Setting Size field (DMCCRn.XFSZ) setting is 8
bytes or more. Refer to “14.3.8.3 Double Word Byte Swapping” for more
information.
1: Reverses the byte order.
0: Does not reverse the byte order.
Acknowledge Polarity (Default: 0)
Specifies the polarity of the DMAACK[n] signal.
1: Asserts when the DMAACK[n] signal is High
0: Asserts when the DMAACK[n] signal is Low
Request Polarity (Default: 0)
Specifies the polarity of the DMAREQ[n] signal.
1: Asserts when the DMAREQ[n] signal is High.
0: Asserts when the DMAREQ[n] signal is Low.
Edge Request (Default: 0)
Specifies the method for detecting DMA requests by the DMAREQ[n] signal.
1: DMAREQ[n] signal is Edge Detect.
0: DMAREQ[n] signal is Level Detect.
Chain Done (Default: 0)
Selects control by the DMADONE* signal. See “14.3.3.3” for more
information.
1: Assertion of the DMADONE* signal controls the overall Chain DMA
transfer.
0: Assertion of the DMADONE* signal controls DMA transfer according to the
DMA Channel Register setting at that time.
Done Control (Default: 00)
Specifies the input/output mode of the DMADONE* signal. Refer to “14.3.3.3
DMADONE* Signal” for more information.
00: DMADONE* signal becomes the input signal, but input is ignored.
01: DMADONE* signal becomes the input signal.
10: DMADONE* signal becomes the output signal.
11: DMADONE* signal becomes the open drain input/output signal.
14-25
Toshiba RISC Processor
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TX4939
14
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