TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 331

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DDR
15.1. Features
The DDR SDRAM Controller generates the clock and control signals that are required by the DDR SDRAM interface. The
DDR SDRAM Controller has 2 on-chip channels and can support memory sizes of up to 2 GB (1 GB/Channel) by
supporting various memory configurations.
Rev. 3.1 November 1, 2005
Memory Clock Frequency: from 100 MHz to 200 MHz
2 Independent Memory Channels
Supports 2- or 4-bank 16 Mb, 64 Mb, 128 Mb, 256 Mb, 512 Mb or 1 Gb DDR SDRAM
Can use registered DIMM
Memory data bus width is 32 bits (word or W)
Internal data bus width is 64 bits (double-word or DW)
Supports critical first word access of the TX49/H4 core
Low power consumption mode: Can select Self-refresh or Pre-charge Power Down
Supports DMAC special Burst access (address decrement/fix)
Can write to any byte during Single or Burst Write operation. This feature is controlled by the DQM signal.
Supports burst length of up to 32DWs on GBUS
Programmable Drive Strength for DDR signals
Chapter 15. DDR SDRAM Controller
15-1
Toshiba RISC Processor
TX4939
15
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