TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 354

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DDR
DDR_CTL_18 = 0x8090
DDR_CTL_19 = 0x8098
DDR_CTL_20 = 0x80A0
Rev. 3.1 November 1, 2005
Name
CONCURRENTAP
-
INTRPTREADA
-
Name
INTRPTWRITEA
-
INTRPTAPBURST
-
Name
TRAS_LOCKOUT
-
TRCD_INT
-
Bits
0:0
7:1
8:8
15:9
Bits
0:0
7:1
8:8
15:9
Bits
0:0
7:1
11:8
15:11
Default
0x0
-
0x0
-
Default
0x0
-
0x0
-
Default
0x0
-
0x0
-
Range
0x0-0x1
-
0x0-0x1
-
Range
0x0-0x1
-
0x0-0x1
-
Range
0x0-0x1
-
0x0-0xf
-
15-24
Description
Allow controller to issue commands to other banks while a bank is in
the process of autorefresh.
Enable Concurrent Auto precharge. Some DRAM devices do not
allow one bank to be auto pre charged while another bank is reading
or writing. The JEDEC standard allows concurrent auto precharge.
0 = Concurrent Auto precharge disabled.
1 = Concurrent Auto precharge enabled.
Reserved
Allow the controller to interrupt a read with autoprecharge command
with another read command.
Enable interrupting of a read with auto precharge command with
another read command to the same bank before the first read
command is completed.
0 = Disable interrupting a read with auto precharge with another read
command to the same bank.
1 = Enable interrupting a read with auto precharge with another read
command to the same bank.
Reserved
Description
Allow the controller to interrupt a write command with autoprecharge
with another write command.
Enable interrupting of a write with auto precharge command with
another read or write command to the same bank before the first
write command is completed.
0 = Disable interrupting a write with auto precharge with another read
or write command to the same bank.
1 = Enable interrupting a write with auto precharge with another read
or write command to the same bank.
Reserved
Allow the controller to interrupt a command with autoprecharge with
another command.
Enable interrupting an auto precharge command with another
command for a different bank. If enabled the current operation will
be interrupted but the bank will be pre charged as if the current
operation were allowed to continue.
0 = Disable interrupting an auto precharge operation on a different
bank.
1 = Enable interrupting an auto precharge operation on a different
bank.
Reserved
Description
Allow the controller to execute autoprecharge commands before the
TRAS_MIN parameter has expired.
Tras lockout setting for the DRAM device.
0 = Tras lockout not supported by memory device
1 = Tras lockout supported by memory device
Reserved
DRAM TRCD parameter in cycles.
Ras to Cas delay in cycles
Reserved
Toshiba RISC Processor
TX4939
15
15