TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 358

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DDR
DDR_CTL_37 = 0x8128
DDR_CTL_38 = 0x8130
DDR_CTL_39 = 0x8138
DDR_CTL_40 = 0x8140
DDR_CTL_41 = 0x8148
Rev. 3.1 November 1, 2005
Name
TC300C_WR_DQS_SUB
-
Name
TC300C_DLL_DQS_DELAY_0
-
Name
TC300C_DLL_DQS_DELAY_1
-
Name
TC300C_DLL_DQS_DELAY_2
-
Name
TC300C_DQS_OUT_SUB
-
Bits
4:0
15:5
Bits
4:0
15:5
Bits
8:0
Bits
8:0
Bits
8:0
15:9
15:9
15:9
Default
0x00
-
Default
0x00
-
Default
0x00
-
Default
0x00
-
Default
0x00
-
Range
0x0-0x1f
-
Range
0x0-0x1f
-
Range
0x0-0x1ff
-
Range
0x0-0x1ff
-
Range
0x0-0x1ff
-
15-28
Description
Offset delay subtracted from the TC300C_WR_DQS_SHIFT delay
of the clk_wr signal in the controller.
The number of delay element subtracted from the number calculated
from the TC300C_WR_DQS_SHIFT parameter. This parameter
allows finer control of the exact number of delay element to be used.
Reserved
Description
Offset delay subtracted from the TC300C_DQS_OUT_SHIFT delay
of the write dqs signal to the DRAMs during writes.
The number of delay element subtracted from the number
calculated from the TC300C_DQS_OUT_SHIFT parameters. This
parameter allows finer control of the exact number of delay element
to be used.
Reserved
Description
Fraction of a clock cycle to delay the dqs signal from the DRAMs
during reads.
The number of 1/360ths of the system clock to delay the dqs signals
from the DDR SDRAM devices to center the edges of the dqs signal
to capture the read data in the middle of the valid window. This
parameter controls the amount of delay to introduce to the dqs path
for dq[7:0] of the read data.
Reserved
Description
Fraction of a clock cycle to delay the dqs signal from the DRAMs
during reads.
The number of 1/360ths of the system clock to delay the dqs signals
from the DDR SDRAM devices to center the edges of the dqs signal
to capture the read data in the middle of the valid window. This
parameter controls the amount of delay to introduce to the dqs path
for dq[15:8] of the read data.
Reserved
Description
Fraction of a clock cycle to delay the dqs signal from the DRAMs
during reads.
The number of 1/360ths of the system clock to delay the dqs signals
from the DDR SDRAM devices to center the edges of the dqs signal
to capture the read data in the middle of the valid window. This
parameter controls the amount of delay to introduce to the dqs path
for dq[23:16] of the read data.
Reserved
Toshiba RISC Processor
TX4939
15
15