TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 359

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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DDR
DDR_CTL_42 = 0x8150
DDR_CTL_43 = 0x8158
DDR_CTL_44 = 0x8160
DDR_CTL_45 = 0x8168
DDR_CTL_46 = 0x8170
Following de-assertion of the reset pin, the registers in the controller must be configured before the DRAM devices can be
accessed.
Rev. 3.1 November 1, 2005
Name
TC300C_DLL_DQS_SUB_1
-
Name
TC300C_DLL_DQS_DELAY_3
-
Name
TC300C_DLL_DQS_SUB_0
-
Name
TC300C_DLL_DQS_SUB_2
-
Name
TC300C_DLL_DQS_SUB_3
-
Bits
8:0
15:9
Bits
4:0
Bits
4:0
15:5
Bits
4:0
15:5
15:5
4:0
Bits
15:5
Default
0x00
-
Default
0x00
-
Default
0x00
-
Default
0x00
-
Default
0x00
-
Range
0x0-0x1f
-
Range
0x0-0x1ff
-
Range
0x0-0x1f
-
Range
0x0-0x1f
-
Range
0x0-0x1f
-
15-29
Description
Fraction of a clock cycle to delay the dqs signal from the DRAMs
during reads.
The number of 1/360ths of the system clock to delay the dqs signals
from the DDR SDRAM devices to center the edges of the dqs signal
to capture the read data in the middle of the valid window. This
parameter controls the amount of delay to introduce to the dqs path
for dq[31:24] of the read data.
Reserved
Description
Delay offset subtracted from TC300C_DLL_DQS_DELAY_0 delay
of the dqs signal from the DRAMs during reads.
The number of delay element subtracted from the number
calculated from the TC300C_DLL_DQS_DELAY_0 parameter.
This parameter allows finer control of the exact number of delay
element to be used.
Reserved
Description
Delay offset subtracted from TC300C_DLL_DQS_DELAY_2 delay
of the dqs signal from the DRAMs during reads.
The number of delay element subtracted from the number
calculated from the TC300C_DLL_DQS_DELAY_2 parameter.
This parameter allows finer control of the exact number of delay
element to be used.
Reserved
Description
Delay offset subtracted from TC300C_DLL_DQS_DELAY_3 delay
of the dqs signal from the DRAMs during reads.
The number of delay element subtracted from the number
calculated from the TC300C_DLL_DQS_DELAY_3 parameter.
This parameter allows finer control of the exact number of delay
element to be used.
Reserved
Description
Delay offset subtracted from TC300C_DLL_DQS_DELAY_1 delay
of the dqs signal from the DRAMs during reads.
The number of delay element subtracted from the number
calculated from the TC300C_DLL_DQS_DELAY_1 parameter.
This parameter allows finer control of the exact number of delay
element to be used.
Reserved
Toshiba RISC Processor
TX4939
15
15

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