TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 361

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Toshiba RISC Processor
DDR
TX4939
15.12. Write Data Timing
Some DRAM devices require that the dqs data strobe arrive at the DRAM devices within a window around the clock that the
DRAM receives. Figure 15-11 below describes this relationship. The value for tdqss is specified in fractions of the clock
cycle. Most DRAMs specify these values between +/- 0.25 and 0.2 of a clock cycle. This translates to a valid window of
between 0.4 and 0.5 of a clock cycle.
Figure 15-11 dqs Arrival Window
The data transfer timing from the controller to the DRAM for writes is similar to the read transfer from the DRAMs to the
controller. There are two differences. The first is that the DRAM devices expect the dqs signal to be shifted by the
controller to allow the DRAM the maximum margin for capturing the data with the dqs signal sent to the DRAMs from the
controller. The second condition is that the first rising edge of the dqs signal sent from the controller must occur near the
rising edge of the clk at the DRAM. This is called the arrival window. DRAMs typically specify this window as 0.8clk to
15
15
1.2clk. See Figure 15-12 below for details.
The DLL maintains two delay lines to accomplish the sending of write data and the write dqs strobe:
The first delay line delays the main clock by the amount needed to have the write dqs strobe transition as near to the clock
edge at the DRAM as possible under typical operating conditions. The amount of delay is controlled by the
TC300C_dqs_out_shift and TC300C_dqs_out_sub parameters.
The second delay line adjusts the clock that is used to output the write data. This clock should be adjusted to maximize the
setup and hold requirements around the dqs write strobe. The amount of delay is controlled by the TC300C_wr_dqs_shift
and TC300C_wr_dqs_sub parameters.
Rev. 3.1 November 1, 2005
15-31