TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 363
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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DDR
15.13. DDR Controller Address Mapping
The DDR Databahn memory controller automatically maps the incoming user address to the available DRAM memory
connected to the controller in a contiguous block starting at user address 0 and ending at the highest available address
according to the size and number of DRAM devices connected to the controller. This mapping is determined by the
pre-chosen address mapping of the Chip Select, Row, Bank, Column signals plus setting certain fields in the internal
Databahn registers.
In this controller the address map is ordered as follow:
The Bank, Chip Select, and Datapath widths are fixed while the widths of the other two portions of the memory map are
programmable using the device address width registers in the controller. This width can be reduced from the maximum by
selecting values for the register settings that are less than the maximum configured.
For this controller, the bit width of Chip Select, Row, Bank, Column and Datapath are as follow:
The maximum allowable address space and mapping into the DRAM devices for the controller is shown in Figure 15-13
below. The numbers on top of the map correspond to the address posted to the controller. This map corresponds to a
memory device with 14 row address bits and 12 column bits.
The DDR Databahn memory processor can support memories with address pins widths and column size widths of up to 7
bits less each than the maximum configured. This allows the DDR Databahn memory processor to function with a wide
variety of memory device sizes.
The register settings for addr_pins and column_size control the address map used to decode the user address to the DRAM
chip selects and row and column addresses. It is assumed that the values in these registers never exceed the maximum
values configured. From the above example, if the memory processor is wired to devices with 12 address pins and 10
column bits, the maximum accessible memory space would be 128MB, and the address map is shown in Figure 15-14,
“Alternate memory map,” below. Note that address bits 30 through 27 are not used. These bits are ignored when
generating the address to the DRAMs.
Rev. 3.1 November 1, 2005
Chip Select, Row, Bank, Column, Datapath
Chip Select = 1
Row = 14
Bank = 2
Column = 12
Datapath = 2
30
Don’t Care
30
Chip Select
27
26
Chip Select
Figure 15-13 Controller Memory Map: Maximum
29
Row
Figure 15-14 Alternate Memory Map
25
Row
16
15
Bank
15-33
14
13
Bank
14
13
Column
12
11
Column
2
Toshiba RISC Processor
1
dp
2
1
dp
0
0
TX4939
15
15
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