TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 379

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.3.11. 66 MHz Operation Mode
The TX4939 PCI Controller supports 66 MHz PCI. The way the TX4939 decides whether to operate the PCI in 33/66 MHz
mode is described below.
The clock for the internal PCI Bus is always at 66MHz.
It is possible to read the state of the external PCI Bus clock from the 66 MHz Drive Status bit (P2GSTATUS.M66EN) of the
P2G Status Register.
PCI Controller can be reset by either the TX4939 Master Reset or PCI hardware reset register.
The software uses a hardware reset (PCICCFG.HRST of the PCI Controller Configuration Register) to reset the PCI
Controller. The PCIRST signal to external devices can be asserted when asserting EPCIRST bit in clock control register.
16.3.12. Power Management
The TX4939 PCI Controller supports power management functions that are compliant to PCI Bus Power Management
Interface Specifications Version 1.1.
The PCI Host device controls the system status by reporting the power management state to the PCI Satellite device. Also,
the PCI Satellite device uses the PME* signal to report requests for changing the power management state or to report to the
PCI Host device that a power management event has occurred.
16.3.12.1. Power Management State
In the case of the PCI Bus Power Management Interface Specifications, four power management states are defined from
State D0 to State D3. The TX4939 supports states D0 through D3. Figure 16-11 illustrates the power management state
transition.
After Power On Reset, or when transitioning from the D3
uninitialized D0. If initialized by the system software at this point, the state transitions to D0 Active.
The TX4939 uses the software to change the system status after a status change is detected.
Rev. 3.1 November 1, 2005
□ The M66EN pin is a ground pin in 33MHz card connectors.
□ If there is no 33MHz card connected to the PCI system, then this pin remains un-driven high.
□ If at least one card connected to the PCI system is a 33MHz connector, then the ground track at the place of
□ The TX4939 PCI clock generator detects the polarity of the M66EN signal. If the M66EN signal is pulled high,
M66EN pin position pulls the M66EN signal down.
the clock generator generates 66MHz clock, else if it is low, it generates 33 MHz clock.
Power On Reset
D0 Active
(RESET*)
System Software
Initialization by
Figure 16-11 Transition of the Power Management States
Power State
Changed
PMCSR
Uninitialized
16-15
HOT
D3
state to the D0 state, the power management state becomes
D0
Software
HOT
Reset
PCI RST
(RESET
Cut-off
D3
VCC
Toshiba RISC Processor
COLD
* )
*
*
*
TX4939
16
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