TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 380

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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PCIC
16.3.12.2. PME* Signal (Satellite Mode) [Note This Function is Disabled]
The following PMEs (Power Management Events) are reported when in the Satellite mode.
16.3.12.3. PME* Signal* (Host Mode)
The PME Detection bit (PCICSTATUS.PMED) of the PCI Controller Status Register is set when an external satellite device
asserts the PME* signal while the TX4939 is in the Host mode. It is also possible to generate PME Detection interrupts at this
time.
Rev. 3.1 November 1, 2005
□ The PCI Host device sets the PME_En bit of the PMCSR Register in the TX4939 configuration space. This
□ Then, the PME_En Set bit (P2GSTATUS.PMEES) of the P2G Status Register is set. Furthermore, it also
□ Writing “1” to the PME bit (P2GCFG.PME) of the P2G Configuration Register sets the PME_Status bit of the
□ The PCI Host device checks the PMCSR PME_Status bit of each PCI device, then specifies the PCI device
□ After the process corresponding to PME ends, the PCI Host device writes “1” to the TX4939 PME_Status bit
□ The TX4939 software should then check the PMCSR PME_Status bit of each PCI device on PCI Bus to
□ Once the device which asserted the PME* signal is identified, then the process (routine to service the PME*
□ After the process corresponding to PME ends, the TX4939 writes “1” to the PME_Status bit of the PCI
makes it possible for the TX4939 to assert the PME* signal.
becomes possible to generate PME_En Set interrupts. The PME_En bit value can be read from the PME_En
bit (PCISSTATUS.PMEEN) of the Satellite Mode PCI Status Register.
PMCSR Register, then asserts the PME* signal, which is the open drain signal. PME is then reported to the
PCI Host device.
that asserted the PME* signal.
that reported PME, thereby reporting the end of the process. As a result, the PME_Status bit of the PMCSR
Register is cleared and the PME* signal is deasserted.
Then, the PME Status Clear bit (P2GSTATUS.PMECLR) of the P2G Status Register is set. It is also possible
to generate PME Status Clear interrupts.
detect which PCI device asserted the PME* signal.
assertion) corresponding to the PCI device which asserted the PME* should be started by the TX4939
software.
device that reported PME, thereby reporting the end of the process. As a result, the PME_Status bit of the
PMCSR Register in the PME reporting PCI device is cleared and the PME* signal is deasserted.
16-16
Toshiba RISC Processor
TX4939
16
16

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