TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 383
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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PCIC
16.3.13.3. Dynamic Chain Operation
It is possible to dynamically add other DMA Command Descriptor Chains to a DMA Command Descriptor Chain that is
currently being processed when executing DMA data transfer. This is done according to the following procedure.
16.3.13.4. Data Transfer Size
The Transfer Size field (PDMCFG.XFERSIZE) of the PDMAC Control Register specifies the transfer size of each G-Bus
transaction in a DMA transfer. The transfer size can be selected from one of the following: 1 DWORD, 1 QWORD, or 4
QWORD (Burst transfer).
1 QWORD or 4 QWORD can only be selected as the transfer size when the setting of the PDMAC G-Bus Address Register
(PDMGA) and the PDMAC PCI Bus Address Register (PDMPA) is a 64-bit address boundary and the PDMAC Count
Register (PDMCTR) setting is an 8-byte multiple. 1 DWORD must be selected as the transfer size in all other cases.
Rev. 3.1 November 1, 2005
(1)
(2)
(3)
DMA Command Descriptor Chain Construction
Constructs a DMA Command Descriptor Chain in memory.
Addition of DMA Command Descriptor Chains
Substitutes the address of the command descriptor that is at the beginning of the descriptor chain to
be added into the Descriptor Chain Address field at the end of the DMA Command Descriptor Chain
that is currently performing DMA transfer.
Chain Enable bit checking
Reads the value of the Chain Enable bit (CHNEN) in the PDMAC Control Register (PDMCFG). If the
read value is “0”, then the Chain Address field value of the DMA Command Descriptor indicated by
the address stored in the PDMAC Chain Address Register (PDMCA) is written to the PDMAC Chain
Address Register (PDMCA)
16-19
Toshiba RISC Processor
TX4939
16
16
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