TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 385

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.3.15. PCI Bus Arbiter
Configuration settings during boot up select whether to use the on-chip PCI Bus arbiter (Internal PCI Bus Arbiter mode) or
to use the External PCI Bus arbiter (External PCI Bus Arbiter mode).
When in the Internal PCI Bus Abiter mode, setting the PCI Bus Arbiter Enable bit (PBACFG.PBAEN) of the PCI Bus Arbiter
Configuration Register starts operation.
The on-chip PCI Bus arbiter can arbitrate eight sets of PCI Bus usage requests from the Bus Master. Seven (7) ports are
used: one for the PCI Controller bus master and six (6) for External Bus masters. The one remaining port is reserved for
future expansion.
16.3.15.1. Request Signal, Grant Signal
The six external Bus Masters are connected to the REQ[5:0] signals and the GNT[5:0]* signals. Also, when in the External
PCI Bus Master mode, the REQ[0]* signal becomes the PCI Bus Request Output signal and the GNT[0]* signal becomes
the Bus Usage Permission Input Signal. Furthermore, the REQ[1]* signal can be used as an interrupt output signal to the
external devices (see 14.3.7 for more information). This is explained in the Figure 16-12.
Rev. 3.1 November 1, 2005
Internal
Internal
Arbiter
Bridge
Bridge
Arbiter
PCI
PCI
PCI
PCI
Gnt_En[7:6]
Gnt_En[7:6]
Gnt_En[5:0]
Gnt_En[5:0]
Req_Out_en
Req_Out_en
Req_[5:0]
Req_[5:0]
Gnt_[5:0]
Gnt_[5:0]
Req_[6]
Figure 16-12 PCI Req/Gnt connections in Int/Ext Arbiter Mode
Gnt_[6]
Req_[6]
Gnt_[6]
Gnt_In
Gnt_In
Req_7
Req_7
Req_Out_
Req_Out_
Gnt_7
Gnt_7
1
1
EPCIINTOE_
EPCIINTOE_
Pci0Req_
Pci0Req_
Pci0Req_en_
Pci0Req_en_
’
’
b1
b1
PCIXARB
PCIXARB
EPCIINT
EPCIINT
4
PCIXARB
4
PCIXARB
4
4
’
’
{4 {4’
b1111
b1111
’
’
b1111
b1111
1
0
1
0
’
1
0
1
0
b1111,EPCIINTOE_,Pci0Req_en_}
b1111,EPCIINTOE_,Pci0Req_en_}
1
1
0
0
Pci0Req_
Pci0Req_
1
1
{4 {4’
pci
pci_
’
’
b1
b1
’
b1111,EPCIINT,Pci0Req_}
b1111,EPCIINT,Pci0Req_}
Pci
Pci_
_
gnt_in_[0]
gnt
6
6
_
’
’
req
req_in_[5:0]
_in_[0]
b111111
b111111
_in_[5:0]
6
6
6
6
’
’
’
’
b111111
b111111
b111111
b111111
16-21
6
6
6
6
’
’
’
’
b111111
b111111
b111111
b111111
PCIXARB
PCIXARB
1
1
1
1
0
0
0
0
PCIXARB
PCIXARB
pci_
pci
1
0
1
0
1
0
1
0
Pci_
Pci
Pci
Pci_
_
gnt_in_[5:0]
gnt
_
_
req_out_[5:0]
Pci_
req
Pci
req
req_en_[5:0]
_in_[5:0]
Pci
Pci_
_
_out_[5:0]
_en_[5:0]
gnt_out_[5:0]
_
gnt
gnt
gnt_en_[5:0]
_out_[5:0]
_en_[5:0]
Toshiba RISC Processor
(Bi
(Bi-
-
Block
Block
Buffers)
Buffers)
Directional
Directional
IO
IO
TX4939
16
16