TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 401

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.4.13. G2P Timeout Count Register (G2PTOCNT)
The Retry Timeout field corresponds to the Retry Timeout Value Register of the PCI Configuration Space, and the TRDY
Timeout field corresponds to the TRDY Timeout Value Register of the PCI Configuration Space.
16.4.14. G2P Status Register (G2PSTATUS)
Rev. 3.1 November 1, 2005
Bits
31:16
15:8
7:0
Default
Default
Default
Default
NAME
NAME
NAME
NAME
Bit
31:2
1
0
TYPE
TYPE
TYPE
TYPE
Mnemonic
RETRYTO
TRDYTO
Mnemonic
IDTTOE
IDRTOE
31
15
31
15
30
14
30
14
Field Name
Reserved
Retry Timeout
TRDY Timeout
Field Name
Reserved
TRDY Timeout
Error
Retry Timeout
Error
29
13
29
13
RETRYTO
28
12
28
12
0x80
R/W
Figure 16-24 G2P Timeout Count Register
Table 16-25 G2P Timeout Count Register
27
11
27
11
Description
Retry Time Out (Default: 0x80)
Sets the maximum number of retries to accept when operating as the initiator
on the PCI Bus. Ends with an error when receiving more retry terminations
than the set maximum number.
Setting a “0” disables this timeout function.
Note:
zero. Some PCI devices invoke more than 128 retries at normal times.
TRDY Time Out (Default: 0x80)
Sets the maximum value of the time to wait for assertion of the TRDY* signal
when operating as the initiator on the PCI Bus.
Setting a “0” disables this timeout function.
Note:
zero. Some PCI devices exhibit a TRDY delay longer than 128 PCI clocks at
normal times.
Figure 16-25 G2P Status Register
Description
Initiator Detected TRDY Time Out Error (Default: 0x0)
This bit is set when the initiator detects a TRDY timeout.
Initiator Detected Retry Time Out Error (Default: 0x0)
This bit is set when the initiator detects a Retry timeout.
Table 16-26 G2P Status Register
26
10
26
10
Generally, disable retry time-out detection by setting this field to
Generally, disable TRDY time-out detection by setting this field to
RESERVED
25
25
9
9
16-37
RESERVED
RESERVED
24
24
8
8
23
23
7
7
22
22
6
6
21
21
5
5
20
20
TRDYTO
Toshiba RISC Processor
4
4
0x80
R/W
19
19
3
3
18
18
2
2
R/W1C R/W1C
IDTTOE IDRTOE
0x0
17
17
1
1
R/W
⎯
R/W
R/W
R/W
⎯
R/W1C
R/W1C
TX4939
0x0
16
16
0
0
16
16