TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 404

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.4.17. PCI Status Interrupt Mask Register (PCIMASK)
Rev. 3.1 November 1, 2005
Default
Default
NAME
NAME
Bit
31:16
15
14
13
12
11
13
12
11
10:9
8
7:0
TYPE
TYPE
Mnemonic
DPEIE
SSEIE
RMAIE
RTAIE
STAIE
RMA
RTA
STA
MDPEIE
DPEIE SSEIE RMAIE RTAIE STAIE
R/W
0x0
31
15
R/W
0x0
30
14
Field Name
Reserved
Detected Parity
Error Interrupt
Enable
Signaled System
Error Interrupt
Enable
Received Master
Abort Interrupt
Enable
Received Target
Abort Interrupt
Enable
Signaled Target
Abort Interrupt
Enable
Received Master
Abort
Received Target
Abort
Signaled Target
Abort
Reserved
Master Data Parity
Detected Interrupt
Enable
Reserved
R/W
0x0
29
13
R/W
0x0
28
12
Figure 16-28 PCI Status Interrupt Mask Register
Table 16-29 PCI Status Interrupt Mask Register
R/W
0x0
27
11
Description
Detected Parity Error Interrupt Enable (Default: 0x0)
Generates an interrupt when a parity error is detected.
Usually, this interrupt is masked and a Master Data Parity error signals the
error to the system.
1: Generates an interrupt.
0: Does not generate an interrupt.
Signaled System Error Interrupt Enable (Default: 0x0)
Generates an interrupt when a system error is signaled.
1: Generates an interrupt.
0: Does not generate an interrupt.
Received Master Abort Interrupt Enable (Default: 0x0)
Generates an interrupt when a Master Abort is received.
1: Generates an interrupt.
0: Does not generate an interrupt.
Received Target Abort Interrupt Enable (Default: 0x0)
Generates an interrupt when a Target Abort is received.
1: Generates an interrupt.
0: Does not generate an interrupt.
Signaled Target Abort Interrupt Enable (Default: 0x0)
Generates an interrupt when a Target Abort is signaled.
1: Generates an interrupt.
0: Does not generate an interrupt.
Received Master Abort (Default: 0x0)
This is a shadow register of the PCISTATUS.RMA bit.
Received Target Abort (Default: 0x0)
This is a shadow register of the PCISTATUS.RTA bit.
Signaled Target Abort (Default: 0x0)
This is a shadow register of the PCISTATUS.STA bit.
Master Data Parity Detected Interrupt Enable (Default: 0x0)
Generates an interrupt when data parity is detected.
1: Generates an interrupt.
0: Does not generate an interrupt.
26
10
Reserved
25
9
16-40
MDPEIE
RESERVED
R/W
0x0
24
8
23
7
22
6
21
5
RESERVED
20
Toshiba RISC Processor
4
19
3
18
2
17
1
R/W
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
⎯
R/W
⎯
TX4939
16
0
16
16