TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 425

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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PCIC
16.4.42. PCI Controller Configuration Register (PCICCFG)
Rev. 3.1 November 1, 2005
Default
Default
NAME
NAME
Bit
31:28
27:16
15:12
11
10
TYPE
TYPE
Mnemonic
GBWC
HRST
SRST
31
15
RESERVED
RESERVED
30
14
Field Name
Rsvd
G-Bus Wait
Counter Setting
Rsvd
Hardware Reset
Software Reset
29
13
Figure 16-53 PCI Controller Configuration Register
Table 16-54 PCI Controller Configuration Register
28
12
HRST SRST IRBER G2PM0EN G2PM1EN G2PM2EN G2PIOEN TCAR ICAEN LCFG
R/W
0x0
27
11
Description
G Bus Wait Counter (Default: 0xFFF)
Sets the Retry response counter at the G-Bus during a PCI initiator Read
transaction.
When the initiator Read access cycle exceeds the setting of this counter, a
Retry response is sent to the G-Bus and the G-Bus is released. PCI Read
operation continues. This counter uses the G-Bus clock (GBUSCLK) when
operating.
When 0x000 is set, a Retry response is not sent to the G-Bus by a long
response cycle count.
When the G-Bus timeout count is used with the value other than the initial
value 4096 GBUSCLK, G-BUS timeout may occur before a Retry response is
sent.
When G-Bus timeout of the configuration register (CCFG.GTOT) is used with
the value other than the initial value (11), set the following maximum values to
the register.
GTOT value Maximum value of the register
Hard Reset (Default: 0x0)
Performs PCI Controller hardware reset control. This bit is automatically
cleared when Reset ends. This is a diagnostic function.
The PCI Controller cannot be accessed for 32 G-Bus clock cycles after this bit
is set.
1: Perform a hardware reset on the PCI Controller.
0: Do not perform a hardware reset on the PCI Controller.
Soft Reset (Default: 0x0)
Performs PCI Controller software reset control. Data is also reloaded to the
Configuration Space Register from the Configuration Data Register. Please
set this bit after the EEPROM Load End bit (PCICSTATUS.E2PDONE) is set.
Also, please use the software to clear this bit at least four PCI Bus Clock
cycles after Reset.
Other registers of the PCI Controller cannot be accessed while this bit is set.
This bit differs from the Hardware Reset bit (HRST). The following register
values are not initialized.
G2P Status Register (G2PSTATUS)
PCI Bus Arbiter Status Register (PBASTATUS)
PCI Controller Status Register (PCICSTATUS)
Software Reset bit (PCICCFG.SRST)
Load Configuration Register bit (PCICCFG.LCFG)
1: The PCI Controller is reset by the software.
0: The PCI Controller is not reset by the software.
10 (2048 GBUSCLK) :
01 (1024 GBUSCLK) :
00 ( 512 GBUSCLK) :
R/W
0x0
26
10
R/W
0x1
25
9
16-61
R/W
0x0
24
8
R/W
0x0
23
7
0x7f0
0x3f0
0x1f0
R/W
0x0
22
6
0xFFFF
GBWC
R/W
R/W
0x0
21
5
R/W
0x0
20
Toshiba RISC Processor
4
R/W
0x0
19
3
R/W
0x0
18
2
17
Reserved
1
R/W
R/W
R/W
R/W
TX4939
16
0
16
16

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