TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 431

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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PCIC
16.4.46. P2G Memory Space 1 G-Bus Base Address Register (P2GM1GBASE)
Rev. 3.1 November 1, 2005
Default
Default
Default
Default
NAME
NAME
NAME
NAME
Bit
63:39
38
37
36
35:29
28:24
23:0
TYPE
TYPE
TYPE
TYPE
Mnemonic
P2GM1EN
BSWAP
EXFER
BA[35:29]
63
47
31
15
BA[31:29]
62
46
30
14
Field Name
Rsvd
Memory Space 1
Enable
Byte Swap
Endian Transfer
Memory Space
Base Address 1
Rsvd
Rsvd
Figure 16-57 P2G Memory Space 1 G-Bus Base Address Register
Table 16-58 P2G Memory Space 1 G-Bus Base Address Register
61
45
29
13
60
44
28
12
0x00
RESERVED
R/W
59
43
27
11
Description
Target Memory Space 1 Enable (Default: 0x0) Controls whether Memory
Space 1 for target access is valid or invalid.
When this bit is set to invalid, Writes to the Memory Space 1 Lower Base
Address Register or the Memory Space 1 Upper Base Address Register of
the PCI Configuration Register become invalid. Also, “1” is returned to Reads
as a response.
1: Validates Memory Space 1 for target access.
0: Invalidates Memory Space 1 for target access.
Byte Swap Disable
(Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte
swapping of Memory Space 1 for target access.
1: Do not perform byte swapping.
0: Perform byte swapping.
Please use the default state in most situations. If this bit is changed to “1”
when in the Big Endian Mode, the byte order of transfer to Memory Space 0
through DWORD (32-bit) access will not change.
See detail in 16.3.10 Endian Switching Function
Endian Transfer
(Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1)
Sets the Endian Transfer of Memory Space 1 for target access.
1: Performs Endian Transfer.
0: Does not perform Endian Transfer.
Please use the default state.
See detail in 16.3.10 Endian Switching Function
Base Address 0 (Default: 0x000)
Sets the G-Bus base bus address of Memory Space 1 for target access. Can
set the base address in 512-MB units.
58
42
26
10
57
41
25
9
16-67
RESERVED
RESERVED
56
40
24
8
55
39
23
7
P2GM1EN BSWAP EXFER
R/W
0x0
54
38
22
6
0x0/0x1 0x1/0x0
R/W
53
37
21
5
RESERVED
R/W
52
36
20
Toshiba RISC Processor
4
51
35
19
3
50
34
18
BA[35:32]
2
R/W
0x0
49
33
17
1
R/W
R/W
R/W
R/W
R/W
R/W
TX4939
48
32
16
0
16
16

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