TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 442

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.4.60. PDMAC Count Register (PDMCTR)
Rev. 3.1 November 1, 2005
Default
Default
Default
Default
NAME
NAME
NAME
NAME
Bits
63:24
23:2
1:0
TYPE
TYPE
TYPE
TYPE
Mnemonic
PDMCTR
63
47
31
15
62
46
30
14
Field Name
Rsvd
Transfer Byte
Count
Rsvd
61
45
29
13
RESERVED
60
44
28
12
59
43
27
11
Description
PDMAC Transfer Count (Default is undefined)
Sets an uncoded 24-bit transfer byte count in 32-bit word units. Also, the
setting of this register must always be a multiple of the transfer size specified
inside the PDMAC Control Register. No data transfer is performed if a count
of “0” is set.
This byte count value is calculated from the transferred byte size as the
PDMAC performs a DMA transfer.
This register value is held without being affected by a Reset.
Figure 16-71 Count Register
Table 16-73 Count Register
58
42
26
10
PDMCTR[15:2]
57
41
25
Undefined
9
16-78
R/W
RESERVED
RESERVED
56
40
24
8
55
39
23
7
54
38
22
6
53
37
21
5
PDMCTR[23:16]
Undefined
52
36
20
Toshiba RISC Processor
4
R/W
51
35
19
3
50
34
18
2
49
33
17
Reserved
1
R/W
⎯
R/W
⎯
TX4939
48
32
16
0
16
16