TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 463

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ATA100
<CAUSION>
The write to the register by the Device/Head register may cause an unexpected function by write wrong
data to the register. So please rewrite to the System Control register after write to the Device/Head
register to secure write to System Control register in ATA100 Core.
Rev. 3.1 November 1, 2005
BIT
Bit[7:4]:
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:
NAME
Data Transfer Mode
Select [3:0]
Break Enable
End Break
Auto DMA Enable
Access Now
Description
You can use this field to select the data transfer mode that the system uses.
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010:
1011:
1100:
1101:
1110-1111: Reserved
The cycle times mentioned above are specific values.
You can suspend PIO Mode data transfer. When setting this bit, you can suspend in
units of the set sector count data transfer that was initiated by the READ MULTIPLE,
READ MULTIPLE EXT, WRITE MULTIPLE, or WRITE MULTIPLE EXT command, and
you can suspend in 512-byte units data transfer that was initiated by all other
commands. Then an interrupt is issued. You can restart transfer by setting bit [2](End
Break). In other words, set bit [3] when initializing and set both bit [2] and bit [3] when
restarting.
While data transfer is suspended by this bit, you can access the device ATA Registers.
When bit [3](Break Enable) has interrupted transfer as described above, setting this bit
makes it possible to clear the suspend state. During a read, this bit is the status bit that
indicates transfer is being suspended.
You can automatically set the transfer direction or initiate transfer when setting this bit
while using one of the following commands to execute data transfer: READ DMA, READ
DMA EXT, WRITE DMA, WRITE DMA EXT. However, the Data Transfer Mode selected
by bits [7:4] must select Multiword DMA or Ultra DMA mode.
The internal State Machine indicates that a device is currently being accessed.
Table 17-1 System Control Register
Selects PIO Mode 0 (Cycle Time: 600 ns)
Selects PIO Mode 1 (Cycle Time: 383 ns)
Selects PIO Mode 2 (Cycle Time: 240 ns)
Selects PIO Mode 3 (Cycle Time: 180 ns)
Selects PIO Mode 4 (Cycle Time: 120 ns)
Selects Multiword DMA Mode 0 (Cycle Time: 480 ns)
Selects Multiword DMA Mode 1 (Cycle Time: 150 ns)
Selects Multiword DMA Mode 2 (Cycle Time: 120 ns)
Selects Ultra DMA Mode 0 (16.6) (Cycle Time: 240 ns)
Selects Ultra DMA Mode 1 (25.0) (Cycle Time: 160 ns)
Selects Ultra DMA Mode 2 (33.3) (Cycle Time: 120 ns)
Selects Ultra DMA Mode 3 (44.4) (Cycle Time: 90 ns)
Selects Ultra DMA Mode 4 (66.6) (Cycle Time: 60 ns)
Selects Ultra DMA Mode 5 (100.0) (Cycle Time: 40 ns)
17-9
Toshiba RISC Processor
TX4939
17
17