TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 485

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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ATA100
17.5.2. When read command is issued to the device (Transfer End Position)
The above figure is a timing diagram that shows the transfer end position during read transfer by Ultra DMA Mode 5.
Following is the flow of each control signal at the transfer end position.
The following table shows the parameters when transfer ends.
Rev. 3.1 November 1, 2005
Mode0
Mode1
Mode2
Mode3
Mode4
Mode5
Mode
A- Set DIORN to “1” when all data for the set Sector Count × 512 Bytes is sent to the controller.
B- Wait for the specified time, then set DIOWN to “1”.
C- Wait until DMARQ is cleared.
D- CRC data generated inside the Controller is transmitted to the ATA Data Bus.
E- Set DMACKN to “1”. The device will then latch the CRC data that is transmitted from this controller.
F- Release CS0N, CS1N and HA.
ATA_CLK
HA
CS1N
CS0N
DMARQ
DMACKN
DIOWN
DIORN
IORDY
ATD_IN
180 nsec
150 nsec
140 nsec
140 nsec
140 nsec
140 nsec
DIORN “1” -
DIOWN “1”
Table 17-12 Parameters when Ultra DMA Transfer Ends
130-140 nsec
120-130 nsec
100-110 nsec
90-100 nsec
70-80 nsec
60-70 nsec
DMACKN “1”
DMARQ “0”-
40 nsec
40 nsec
40 nsec
40 nsec
40 nsec
40 nsec
- HA,CS Release
DMACKN “1”
17-31
240 nsec (Min)
160 nsec
(Min)
120 nsec
(Min)
90 nsec
(Min)
60 nsec
(Min)
40 nsec
(Min)
IORDYN cycle
(Input Signal)
90 nsec
80 nsec
60 nsec
50 nsec
30 nsec
20 nsec
Toshiba RISC Processor
Setup (Min.)
CRC Data
30 nsec
30 nsec
30 nsec
30 nsec
30 nsec
30 nsec
CRC Data
Hold
TX4939
17
17

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