TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 486

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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ATA100
17.5.3. When Write Command is issued to the device (Transfer Start Position)
ATA_CLK
HA
CS1N
CS0N
DMARQ
DMACKN
DIOWN
DIORN
IORDY
ATD_OUT
The above figure is timing diagram that shows the transfer start position during write transfer by Ultra DMA Mode 5. The
steps for setting up the software used when transferring data are exactly the same as for when issuing a read command. The
meaning of each signal on the ATA Bus changes: IORDY becomes the transfer Ready signal that the device provides to this
controller; DIORN becomes the Strobe signal when transferring data to the device.
Following is the flow of each control signal at the transfer start position.
The following table shows the parameters when transfer starts.
Rev. 3.1 November 1, 2005
Mode0
Mode1
Mode2
Mode3
Mode4
Mode5
Mode
A- Wait until DMARQ becomes active (“High”).
B- When transfer preparations inside the Controller are complete, set HA to “0h”, and CS0N and CS1N to “1”.
C- Wait for the specified time, then make the DMACKN active (“0”).
D- Wait until IORDY becomes active (“Low”).
E- Wait for the specified time, then transfer data to the device while changing the state of DIORN.
40 nsec
40 nsec
40 nsec
40 nsec
40 nsec
40 nsec
HA, CS Valid -
DMACKN “0”
Table 17-13 Parameters when Ultra DMA Transfer Starts
40 nsec
40 nsec
40 nsec
40 nsec
40 nsec
40 nsec
DMACKN “0” -
DIOWN “0”
140-150 nsec
100-110 nsec
80-90 nsec
60-70 nsec
50-60 nsec
40-50 nsec
17-32
IORDY “0” -
DIORN “0”
120 nsec
80 nsec
60 nsec
“H”: 40
“L”: 50
30 nsec
20 nsec
Pulse Width
DIORN
110 nsec
70 nsec
50 nsec
“H”: 30
“L”: 40
20 nsec
10 nsec
Toshiba RISC Processor
ATDBUS
Setup
10 nsec
10 nsec
10 nsec
10 nsec
10 nsec
10 nsec
ATDBUS
Hold
TX4939
17
17

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