TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 487

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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ATA100
17.5.4. When Write Command is issued to the device (Transfer End Position)
The above figure is a timing diagram that shows the transfer end position during write transfer by Ultra DMA Mode 5.
Following is the flow of each control signal.
The following table shows the parameters when transfer ends.
Rev. 3.1 November 1, 2005
Mode0
Mode1
Mode2
Mode3
Mode4
Mode5
Mode
A- Set DIOWN to “1” when all data for the set Sector Count × 512 Bytes is sent from the controller.
B- Wait until DMARQ is cleared and IORDY is cleared.
C- Send the CRC data generated in the controller to the ATA data bus.
D- Wait for the specified time, then set DMACKN to “1”. The device now latches the CRC data sent from this
E- Release CS0N, CS1N and HA.
controller.
ATA_CLK
HA
CS1N
CS0N
DMARQ
DMACKN
DIOWN
DIORN
IORDY
ATD_OUT
140-150 nsec
130-140 nsec
110-120 nsec
100-110 nsec
80-90 nsec
70-80 nsec
DMACKN “1”
DMARQ “0”-
Table 17-14 Parameters when Ultra DMA Transfer Ends
30 nsec
30 nsec
30 nsec
30 nsec
30 nsec
30 nsec
HA, CS Release
DMACKN “1”-
17-33
100 nsec
90 nsec
70 nsec
60 nsec
40 nsec
30 nsec
Setup (Min)
CRC Data
Toshiba RISC Processor
20 nsec
20 nsec
20 nsec
20 nsec
20 nsec
20 nsec
CRC Data
Hold
TX4939
17
17

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