TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 501

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.3.3. System control model
The Ethernet Controller as two programmable modes: the Interrupt Drive mode and the Polling mode.
By enabling or disabling interrupts for each frame descriptor, the Ethernet Controller can arrange the stage layout to
enable the handling of multiple packets between interrupts. In this way, the ability of the system to handle multiple
packets at once and to cache the handling instructions makes it possible to reduce interrupt handling overhead and
improve performance.
Furthermore, unless major errors occur, you can set the Ethernet Controller to not issue interrupts. In this situation, you
have to put several controls in the Enable state so start/end of traffic and polling in the Idle state is handled efficiently. For
details, see 18.3.9 DMA Operation.
Rev. 3.1 November 1, 2005
Interrupt Drive mode
This mode generates an interrupt each time a packet or group packet transmits or receives.
Polling mode
This mode always polls to see if there is a subsequent packet to transmit or receive. When data or a descriptor
is added to the frame descriptor queue, the Ethernet Controller performs transmission. The Host CPU checks
the status of the frame descriptor for the received packet and judges reception completion. The CPU does not
use an interrupt.
18-9
Toshiba RISC Processor
TX4939
18
18