TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 518

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.3.8.6. Address Recognition Circuit (ARC) operation
To read from or write to ARC memory, first the system software sets the ARC Address Register, and then it reads and
writes the ARC Data Register. All Bytes are written to regardless of the Byte Enable status. To write either the upper 2
Bytes or lower 2 Bytes of a double word, the driver software has to handle the data to correctly and simultaneously write
2 adjoining Bytes. The Ethernet Controller does not support Read, Modify, or Write cycles to internal DMA RAM.
Figure 18-14 shows how the MAC reads entries from the ARC. ARC entries are in the Big Endian Byte order. In other
words, if #0-0 is the first Byte of the first entry, then #0-5 is the sixth and therefore last Byte of the first entry. After entry
#20 are the 2 Bytes Rsv-2 and Rsv-3, then the 2 double words MC#1 and MC#2. MC#1 and MC#2 cannot be used by
ARC operation, but they are used when generating the MAC control frame. Item 18.3.8.7 Pause operation during full
duplex transfer describes this.
Rev. 3.1 November 1, 2005
MC#1-0
MC#2-0
Byte 3
#18-0
#18-4
#19-2
#20-0
#20-4
#0-0
#0-4
#1-2
#2-0
#2-4
#3-2
#4-0
#4-4
#5-2
Figure 18-14 ARM Memory Map
MC#1-1
MC#2-1
Byte 2
#18-1
#18-5
#19-3
#20-1
#20-5
#0-1
#0-5
#1-3
#2-1
#2-5
#3-3
#4-1
#4-5
#5-3
18-26
MC#1-2
MC#2-2
Byte 1
#18-2
#19-0
#19-4
#20-2
Rsv-2
#0-2
#1-0
#1-4
#2-2
#3-0
#3-4
#4-2
#5-0
#5-4
MC#1-3
MC#2-3
Byte 0
#18-3
#19-1
#19-5
#20-3
Rsv-3
#0-3
#1-1
#1-5
#2-3
#3-1
#3-5
#4-3
#5-1
#5-5
0Ch
1Ch
6Ch
7Ch
00h
04h
08h
10h
14h
18h
20h
70h
74h
78h
80h
84h
...
Toshiba RISC Processor
TX4939
18
18