TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 519

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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EMAC
18.3.8.7. Pause operation during full duplex transfer
18.3.8.7.1. Local Pause operation
To enable Pause operation during full duplex transfer, you have to set a special multicast address for the MAC control
frame in ARC memory and set the corresponding bit in the ARC Enable Register. You can store the special multicast
address for the MAC control frame anywhere in ARC memory, but there are cases where you will have to be careful of
the storage location to optimize the usage efficiency of ARC memory (see 18.3.8.7.2 Remote Pause operation). The
MAC reception circuit recognizes full duplex Pause operation when the following conditions are met.
After recognizing full duplex transfer Pause operation, the MAC reception circuit loads the operand values into the Pause
Count Register then instructs both the MAC and DMA engines to pause when processing of the current packet ends. If
no packet is currently being processed, then both engines immediately pause.
The pause circuit manages the Pause Count Register and counts down the pause time. When the pause time count
becomes 0, the pause circuit issues an instruction to end pausing and operation of the transmission circuit resumes.
If another Pause operation is recognized during Pause operation, the Pause Count Register is reset by a new operand
value. An operand value of 0 will abort the Pause operation currently in progress.
18.3.8.7.2. Remote Pause operation
The program can freely set the MAC control frame of the Ethernet Controller, so even when performing Pause operation
or using MAC control in the future, it will still support this function.
For remote Pause operation or transmission of other MAC control frames, follow the procedure below.
Usually, the recipient address is the special multicast address of the MAC control frame and the sender address is the
local station address. You can enable these ARC entries to be used for address filtering. Since ARC entry #20 does not
include a valid network address, you must not enable it when using it as part of a flow control transmission.
When transmission ends, the transmission status is written in the Transmission Control Frame Status Register. If the End
of Transmission Control bit (bit 10) of the Interrupt Enable Control Register is set, the DMA engine will issue interrupts.
Rev. 3.1 November 1, 2005
A particular value (0x8808) is set in the Frame Length/Frame Type field of the MAC control frame.
The ARC recognizes a packet.
The packet is 64 Bytes long.
The Operation field specifies Pause operation (0x0001).
Set the recipient address to #0 of the ARC memory.
Set the sender address to #1 of the ARC memory.
To #20 of the ARC memory set the special MAC control type value (0x0808), the Pause operation opcode
(0x0001), and the operand value (pause time: 0x0000 to 0xFFFF). Write 0x0000 to the 2 Bytes after ARC #20.
Write 0x0000_0000 to MC#1 and MC#2. Then, remote Pause transmission is complete at one bus operation.
Write to the Transmission Control Register and set the SdPause bit.
18-27
Toshiba RISC Processor
TX4939
18
18

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