TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 528

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.4.1.3. Overview of DMA Control, Status Registers
Table 18-8 shows the name, mnemonic, address, size, and access type of each DMA Control, Status Register. DMA
Control, Status Registers control the transmission queue, reception queue, free buffer list, and free descriptor area.
Registers for controlling the fragment size and polling rate are also available.
18.4.1.4. Overview of MAC Control, Status Registers
MAC layer registers are broken down into the Flow Control Register and MAC Control, Status Register groups.
Table 18-9 shows the name, mnemonic, address, size, and access type of each Flow Control Register.
Table 18-10 shows the name, mnemonic, address, size, and access type of each MAC Control, Status Register. Similar
to the ARC Control Register and Error Count Register, some registers are accessed by the system software driver when
the MAC is activated. A standard DMA engine controls the MAC Transmission Control Register, MAC Transmission
Status Register, MAC Reception Control Register, and MAC Reception Status Register after the system software driver
sets them up.
MAC layer Control Registers include registers such as the Master MAC Control Register, Transmission/ Reception
Control Register, and the ARC Control Register.
Rev. 3.1 November 1, 2005
Address
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
Address
30h
34h
38h
Address
40h
44h
48h
4Ch
50h
54h
58h
5Ch
60h
64h
68h
7Ch
Mnemonic
DMA_Ctl
TxFrmPtr
TxThrsh
TxPollCtl
BLFrmPtr
RxFragSize
Int_En
FDA_Bas
FDA_Lim
Int_Src
Mnemonic
PauseCnt
RemPauCnt
TxConFrmStat
Mnemonic
MAC_Ctl
ARC_Ctl
Tx_Ctl
Tx_Stat
Rx_Ctl
Rx_Stat
MD_Data
MA_CA
ARC_Adr
ARC_Data
ARC_Ena
Miss_Cnt
Table 18-8 DMA Control, Status Registers
Table 18-10 MAC Control, Status Register
Table 18-9 Flow Control Registers
18-36
Register Name
DMA Control Register
Transmission Frame Pointer
Transmission Threshold Register
Transmission Polling Control Register
Buffer List Frame Pointer
Reception Fragment Size Register
Interrupt Enable Register
Free Descriptor Area Base Register
Free Descriptor Area Size Register
Interrupt Function Register
Register Name
Pause Count Register
Remote Pause Count Register
Transmission Control Frame Status Register
Register Name
MAC Control Register
ARC Control Register
Transmission Control Register
Transmission Status Register
Reception Control Register
Reception Status Register
Station Management Data Register
Station Management Control, Address Register
ARC Address Register
ARC Data Register
ARC Enable Register
Missed Error Count Register
Toshiba RISC Processor
TX4939
18
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