TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 548

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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EMAC
18.4.3.8. Free Descriptor Area (FDA) Registers
Free Descriptor Area Base Register (FDA_Bas) 0x1C
Hardware resets initialize the Free Descriptor Area Base Register to 0x0000_0000. Software resets do not change the
register contents.
Free Descriptor Area Size Register (FDA_Lim) 0x20
Hardware resets initialize the Free Descriptor Area Size Register to 0x0000_0000. Software resets do not change the
register contents.
Rev. 3.1 November 1, 2005
Bits
31 : 4
3 : 0
Bits
31 : 16
15 : 4
3 : 0
Default
Default
Default
Default
Name
Name
Name
Name
TYPE
TYPE
TYPE
TYPE
Note:
31
15
31
15
Mnemonic
Mnemonic
Count/Offset
You have to specify in the FDA_Lim Register the minimum offset value of the free descriptor area
from which it is safe to start the next frame descriptor. You have to secure an area that is sufficient for
storing a maximum size packet that includes one frame descriptor and the maximum number of buffer
descriptors. For example, if the maximum number of buffer descriptors required to store a maximum
length frame is 28, then this area requires a capacity of 256 (16 + 28 × 8 in 16-Byte units) Bytes.
30
14
30
14
29
13
29
13
Field Name
Address
Reserved
Field Name
Reserved
Count/Offset
Reserved
28
12
28
12
Figure 18-40 Free Descriptor Area Base Register
Figure 18-41 Free Descriptor Area Size Register
27
11
27
11
Count/Offset
26
10
26
10
0x000
0x000
R/W
R/W
Addr
25
25
9
9
18-56
RESERVED
Description
Addr (Default: 0x000_0000, R/W)
The Free Descriptor Area Base Register contains the start
address of the area for writing the frame descriptors and buffer
descriptors of reception packets. The address must be a multiple
of 16 Bytes. Therefore, bits 0-3 are fixed to "0".
Description
Count/Offset (Default: 0x000, R/W)
This field sets the size of the Reception Descriptor Area in 16-
Byte units. You could also consider the lower 16 bits as being an
offset from the base address.
24
24
8
8
0x0000
Addr
R/W
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
Toshiba RISC Processor
19
19
3
3
RESERVED
RESERVED
18
18
2
2
17
17
1
1
TX4939
16
16
0
0
18
18

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