TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 549

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.4.3.9. Interrupt Source Register (Int_Src)
Writing "1" to W1Clr clears it to "0". This bit denotes the bits that clear interrupts. Any writing of "0" to these bits is ignored.
"R" indicates that a bit is Read Only. Either clearing the source that set these bits to "1" or resetting Ethernet control
clears these bits to "0".
Software resets initialize the Interrupt Source Register to 0x0000_0000.
The system software reads the Interrupt Source Register to check whether there are any interrupts related to Ethernet
control. Also, the Interrupt Source Register contains several status bits that can only be displayed here. If bits 15:0 are all
Rev. 3.1 November 1, 2005
Bit(s)
31 : 17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
Default
Name
Name
TYPE
TYPE
Reserved NRAbt DmParErrStat BLEx FDAEx IntNRAbt IntTxCtlCmp IntExBD DmParErr IntEarNot SWInt IntBLEx IntFDAEx IntPCI IntMacRx IntMacTx
31
15
Mnemonic
IntEXDefer
NRAbt
DmParErrStat
BLEx
FDAEx
IntNRAbt
IntTxCtlCmp
IntExBD
DmParErr
IntEarNot
SWInt
IntBLEx
IntFDAEx
IntPCI
IntMacRx
IntMacTx
R/W1
30
14
C
0
R/W1
29
13
C
0
Field Name
Reserved
Reserved
R/W1
28
12
C
0
R/W1
Figure 18-42 Interrupt Source Register
27
11
C
0
26
10
R
0
R/W1
25
C
9
0
18-57
R/W1
Description
IntEXDefer (Default: 0, R/W1C)
This bit is set if an excessive delay is detected and the
EnExDefer (Excessive Defer Enable) bit of the Transmission
Control Register (Tx_Ctl) is set.
NRAbt (Default: 0, R/W1C)
This bit is set to "1" when a non-recoverable abort occurs.
DmParErrStat (Default: 0, R/W1C)
This bit is set to "1" when a DMA parity error occurs.
BLEx (Default: 0, R/W1C)
This bit is set to "1' when the buffer list (BL) becomes full.
FDAEx (Default: 0, R/W1C)
This bit is set to "1" when the free descriptor area (FDA)
becomes full.
IntNRAbt (Default: 0, R)
The interrupt source is a non-recoverable abort state.
IntTxCtlCmp (Default: 0, R/W1C)
The interrupt source is the completion of MAC control frame
transmission.
IntExBD (Default: 0, R/W1C)
The interrupt source is excessive buffer descriptors (more than
28 buffer descriptors).
DmParErr (Default: 0, R)
The interrupt source is a DMA parity error.
IntEarNot (Default: 0, R/W1C)
The interrupt source is early notification.
SWInt (Default: 0, R)
The interrupt source is a software interrupt request.
IntBLEx (Source: 0, R)
The interrupt source is the buffer list being completely used up.
IntFDAEx (Default: 0, R)
The interrupt source is the free descriptor area being completely
used up.
IntPCI (Default: 0, R)
The PCI Status Register (PCI_Stat) displays the interrupt source.
IntMacRx (Default: 0, R/W1C)
The MAC Reception Status Register (Rx_Stat) displays the
interrupt source.
IntMacTx (Default: 0, R/W1C)
The MAC Transmission Status Register (Tx_Stat) displays the
interrupt source.
24
C
8
0
0x24
23
R
7
0
R/W1
22
C
6
0
21
R
5
0
20
R
4
0
Toshiba RISC Processor
19
R
3
0
18
R
2
0
R/W1
17
C
1
0
TX4939
IntEXDefer
R/W1
R/W1
16
C
C
0
0
18
18