TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 555

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.4.5.3. Transmission Control, Status Registers
Transmission Control Register (Tx_Ctl) 0x48
Hardware resets initialize the Transmission Control Register to 0x0000. Software resets clear the TxEn bit, but do not
clear any other bits. Do not set the FBack (Fast Back-off) bit to "1" when in the normal operation mode.
The SdPause (Pause Transmission) bit is automatically cleared when transmission of the MAC control frame ends. Any
writing of "0" to this bit is ignored.
To issue an interrupt for each packet, set the EnComp bit or all MAC Error Enable bits. You can also set interrupts to
occur when a specific state occurs.
Rev. 3.1 November 1, 2005
Bit(s)
31 : 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
Default
Name
Name
TYPE
TYPE
Mnemonic
EnComp
EnTxPar
EnLateColl
EnExColl
EnExDefer
EnUnder
MII10
SdPause
NoExDef
FBack
NoCRC
NoPad
TxHalt
TxEn
31
15
EnComp EnTxPar EnLateColl EnExColl Reserev EnExDefer EnUnder MII10 SdPause NoExDef FBack NoCRC NoPad TxHalt TxEn
R/W
30
14
0
R/W
29
13
Field Name
Reserved
Enable Complete
Enable Transmission
Parity
Enable Late Collisions EnLateColl (Default: 0, R/W)
Enable Excessive
Collisions
Reserved
Enable Excessive
Defer
Underline Enable
MII 10 Mbps Mode
PAUSE Transmission
No Excessive
Deferrals
Fast Back Off
No Suppress
No Padding
Transmission Halt
Request
Transmission Enable
0
R/W
28
12
0
Figure 18-48 Transmission Control Register
R/W
27
11
0
26
10
Description
EnComp (Default: 0, R/W)
Issues an interrupt either when MAC transmits or destroys 1 packet.
EnTxPar (Default: 0, R/W)
Issues an interrupt when a parity error occurs in MAC Transmission FIFO.
Issues an interrupt if a collision occurs after more than 512-bit late time (64-
Byte) time passes.
EnExColl (Default: 0, R/W)
Issues an interrupt if collisions occur in the same packet 16 times.
EnExDefer (Default: 0, R/W)
Issues interrupts when MAC causes a MAX_DEFERRAL time delay.
MAX_DEFERRAL = 0.24288 ms for 100 Mbps
= 2.4288 ms for 10 Mbps
EnUnder (Default: 0, R/W)
Issues an interrupt when the MAC Transmission FIFO becomes empty during
transmission.
MII10 (Default: 0, R/W)
Setting this bit to "1" enables SQE checking.
SdPause (Default: 0, R/W)
Transmits either the Pause command or another MAC control frame.
NoExDef (Default: 0, R/W)
Suppresses excessive deferral checking.
Fback (Default: 0, R/W)
Uses a fast back-off timer during testing.
NoCRC (Default: 0, R/W)
Does not add CRC to the end of a packet.
NoPad (Default: 0, R/W)
Does not generate Pad Bytes even for packets with less than 64 Bytes.
TxHalt (Default: 0, R/W)
Halts transmission if the current packet ends regardless of the packet type.
TxEn (Default: 0, R/W)
Immediately halts transmission when cleared to "0".
R/W
25
9
0
18-63
RESERVED
R/W
24
8
0
R/W
23
7
0
R/W
22
6
0
R/W
21
5
0
R/W
20
4
0
Toshiba RISC Processor
R/W
19
3
0
R/W
18
2
0
R/W
17
1
0
TX4939
R/W
16
0
0
18
18