TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 558

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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EMAC
Hardware resets initialize the Reception Control Register to 0x0000. Software resets clear the RxEn bit, but no other bits
are changed.
To issue an interrupt for each packet, set the EnGood bit or all Error Enable bits. You can also set the Reception Control
Register to only issue interrupts when a particular state occurs.
Rev. 3.1 November 1, 2005
Bit(s)
0
Mnemonic
RxEn
Field Name
Reception Enable
Table 18-11 Reception Control Register
Description
RxEn (Default: 0, R/W)
processing the recipient address, reception operation for the current packet
continues and data is transferred to the system memory. At this time, the
TxHalted bit of the Reception Status Register is set and indicates that the system
issued a Reception Halt Request while receiving a packet.
operation immediately halts. At this time, the RxHalted bit is set.
This bit halts reception when cleared to "0". If this bit is cleared after MAC starts
If this bit is cleared before processing of the recipient address starts, reception
18-66
Toshiba RISC Processor
TX4939
18
18

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