TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 561

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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EMAC
18.4.5.5. Station Management Registers
Station Management Data Register (MD_Data) 0x58
Software resets initialize the Station Management Data Register to 0x0000.
Rev. 3.1 November 1, 2005
Bits
31 : 16
15 : 0
Default
Default
Name
Name
TYPE
TYPE
Mnemonic
31
15
30
14
Field Name
Reserved
Station Management
Data
29
13
28
12
Figure 18-52 Station Management Data Register
27
11
26
10
Description
(Default: 0x0000, R/W )
The MII item of the IEEE802.3 specification that relates the 100Base-T or 100
Mbps Ethernet defines the format of the Stage Management Data Register. For
information on other hardware-dependent registers, see the separate PHY data
sheet.
Station Management Data
25
9
18-69
RESERVED
24
8
0x0000
R/W
23
7
22
6
21
5
20
4
Toshiba RISC Processor
19
3
18
2
17
1
TX4939
16
0
18
18

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