TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 562

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
Station Management Control, Address Register (MD_CA)
Before accessing the PHY Control Register, use the software to check the Busy bit of the Station Management Control,
Address Register and confirm that it is not set.
The Ethernet Controller supports reading or writing of Station Management data to PHY. The setting of the Station
Management Control, Address Register does not affect the operation of the Ethernet Controller.
Rev. 3.1 November 1, 2005
Bit(s)
31 : 12
11
10
9 : 5
4 : 0
Default
Default
Name
Name
TYPE
TYPE
Mnemonic
Busy
Wr
PHY
Addr
31
15
RESERVED
30
14
Field Name
Reserved
Busy Bit
Write
PHY Address
Address
29
13
Figure 18-53 Station Management Control Address Register
28
12
Busy
R/W
27
11
0
R/W
Wr
26
10
0
Description
Busy (Default: 0, R/W)
This bit is set when operation starts. The Ethernet Controller clears this bit when
the operation ends.
Wr (Default: 0, R/W)
This bit is set to "1" during writes and is cleared to "0" during reads.
PHY (Default: 0, R/W)
Address of all PHY to be read or written
Addr (Default: 0, R/W)
Address of PHY-internal register to be read or written.
25
9
18-70
RESERVED
24
8
PHY
0x00
R/W
23
7
0x5C
22
6
21
5
20
4
Toshiba RISC Processor
19
3
Addr
0x00
R/W
18
2
17
1
TX4939
16
0
18
18