TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 565

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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EMAC
ARC Enable Register (ARC _Ena)
Hardware resets initialize the ARC Enable Register to 0x00_0000. Software resets do not change the contents of this
register.
This register indicates which entry to validate as address filtering. This register can validate up to 21 entries numbered
from 0 to 20.
Rev. 3.1 November 1, 2005
Bits
31 : 21
20: 0
Default
Default
Name
Name
TYPE
TYPE
Mnemonic
ARC_Ena
31
15
30
14
Field Name
Reserved
ARC Enable
29
13
28
12
27
11
Figure 18-56 ARC Enable Register
RESERVED
0x68
26
10
Description
ARC_Ena (Default: 0x0_0000, R/W)
Sets the bits corresponding to an entry valid as address filtering.
25
9
18-73
24
ARC_Ena
8
0x0000
R/W
23
7
22
6
21
5
20
4
Toshiba RISC Processor
19
3
ARC_Ena
0x00
R/W
18
2
17
1
TX4939
16
0
18
18

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