TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 591

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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SIO
19.4.9. Receive FIFO Register 0,1,2,3
When using the DMA Controller to perform DMA reception, set the following addresses in the Destination Address Register
(DMDARn) of the DMA Controller according to the Endian Mode bit (DMCCRn.LE) setting of the DMA Controller.
Little Endian: 0xF320 (Ch.0), 0xF360 (Ch.1), 0xF3A0 (Ch.2), 0xF3E0 (Ch.3)
Big Endian:
Rev. 3.1 November 1, 2005
Bit
31:8
7:0
31
15
Mnemonic
RxD
(SIRFIFO0, SIRFIFO1, SIRFIFO2, SIRFIFO3)
Channel
SIO0
SIO1
SIO2
SIO3
0xF323 (Ch.0), 0xF363 (Ch.1), 0xF3A3 (Ch.2), 0xF3E3 (Ch.3)
Field Name
Reserved
Reception
Data
Reserved
Table 19-22 Address offsets for Receive FIFO Register in the TX4939
Address Offset
0xF320
0xF420
0xF3A0
0xF4A0
Description
Receive Data
This field reads reception data from the Receive FIFO.
Reading this register updates the Reception Data Status.
Figure 19-14 Receive FIFO Register
Table 19-23 Receive FIFO Register
Mnemonic
SIRFIFO0
SIRFIFO1
SIRFIFO2
SIRFIFO3
Reserved
8
19-25
7
Register Name
Receive Fifo Register 0
Receive Fifo Register 1
Receive Fifo Register 2
Receive Fifo Register 3
Undefined
RxD
R
Toshiba RISC Processor
16
0
: Initial value
: Initial value
Read/Write
R
: Type
: Type
TX4939
19
19

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