TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 593
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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SPI
20.1. Features
The SPI is a serial interface that consists of clock, data output, and data input. The SPI is used to interface with serial power,
serial A/D converters, other devices including simple serial clocks and data interfaces. The TX4939 only operates as a
Master. It generates SPI clocks to Slaves. Multi-slave devices can share the SPI by using a unique Chip Select for each
Slave device. TX4939 SPI provides a dedicated Chip Select port to access a SPI device.
To access more than one SPI device, the system needs to use other output ports to generate unique Chip Selects. If the
Chip Select of a device is asserted and the device is selected, that device uses the SPICLK and SPIOUT signals to shift data
in, and then uses the SPIIN signal to shift data out. If the device is not selected, the data output connected to SPIIN must be
put into the tri-state and other devices must be able to share the SPIIN signal.
The SPI module contains registers that can program the SPI CLK rate, MSB first or LSB first, clock polarity, data phase
polarity, and Byte mode or Word mode operation.
The SPI module has the following characteristics:
Rev. 3.1 November 1, 2005
Selectable clock phase and polarity
Transfer Size: 8-bit or 16-bit
4-frame Transmitter Buffer and 4-frame Receiver Buffer
Master Operation
Interframe Delay Time Counter
MSB/LSB First
20-1
Chapter 20. SPI Interface
Toshiba RISC Processor
TX4939
20
20
20
20
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